From: Piotr Dymacz Date: Fri, 13 Nov 2015 02:07:23 +0000 (+0100) Subject: Remove old serial and clock drivers, we don't need them anymore X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=07f3c9f4bedf3006930ed371772361032f053fad;p=oweals%2Fu-boot_mod.git Remove old serial and clock drivers, we don't need them anymore --- diff --git a/u-boot/cpu/mips/ar7240/ar7240_serial.c b/u-boot/cpu/mips/ar7240/ar7240_serial.c deleted file mode 100644 index 887094c..0000000 --- a/u-boot/cpu/mips/ar7240/ar7240_serial.c +++ /dev/null @@ -1,240 +0,0 @@ -#include -#include -#include -#include - -#define REG_OFFSET 4 - -/* === END OF CONFIG === */ - -/* register offset */ -#define OFS_RCV_BUFFER (0*REG_OFFSET) -#define OFS_TRANS_HOLD (0*REG_OFFSET) -#define OFS_SEND_BUFFER (0*REG_OFFSET) -#define OFS_INTR_ENABLE (1*REG_OFFSET) -#define OFS_INTR_ID (2*REG_OFFSET) -#define OFS_DATA_FORMAT (3*REG_OFFSET) -#define OFS_LINE_CONTROL (3*REG_OFFSET) -#define OFS_MODEM_CONTROL (4*REG_OFFSET) -#define OFS_RS232_OUTPUT (4*REG_OFFSET) -#define OFS_LINE_STATUS (5*REG_OFFSET) -#define OFS_MODEM_STATUS (6*REG_OFFSET) -#define OFS_RS232_INPUT (6*REG_OFFSET) -#define OFS_SCRATCH_PAD (7*REG_OFFSET) - -#define OFS_DIVISOR_LSB (0*REG_OFFSET) -#define OFS_DIVISOR_MSB (1*REG_OFFSET) - -#define MY_WRITE(y, z) ((*((volatile u32*)(y))) = z) -#define UART16550_READ(y) ar7240_reg_rd((AR7240_UART_BASE+y)) -#define UART16550_WRITE(x, z) ar7240_reg_wr((AR7240_UART_BASE+x), z) - -/* - * This is taken from [Linux]/include/linux/kernel.h - * Keep the name unchanged here - * When this project decides to include that kernel.h some time, - * this would be found "automatically" and be removed hopefully - */ -#define DIV_ROUND_CLOSEST(x, divisor)( \ -{ \ - typeof(divisor) __divisor = divisor; \ - (((x) + ((__divisor) / 2)) / (__divisor)); \ -} \ -) - -/* - * Get CPU, RAM and AHB clocks - * Based on: Linux/arch/mips/ath79/clock.c - */ -void ar7240_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq){ -#ifdef CONFIG_WASP - u32 ref_rate, pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv, cpu_pll, ddr_pll; - - // determine reference clock (25 or 40 MHz) - pll = ar7240_reg_rd(RST_BOOTSTRAP_ADDRESS); - - if(pll & 0x10){ // bit 4 == 1 -> REF_CLK == 40 MHz - ref_rate = 40000000; - } else { - ref_rate = 25000000; - } - - pll = ar7240_reg_rd(DPLL2_ADDRESS_c4); - - // CPU PLL from SRIF? - if(pll & (1 << 30)){ - - out_div = (pll >> 13) & 0x7; - pll = ar7240_reg_rd(0x181161c0); - nint = (pll >> 18) & 0x1ff; - //nfrac = pll & 0x0003ffff; - ref_div = (pll >> 27) & 0x1f; - //frac = 1 << 18; - - } else { - // only for tests - // TODO: fix me - *cpu_freq = 560000000; - *ddr_freq = 400000000; - *ahb_freq = 200000000; - return; - } - - cpu_pll = (ref_rate / ref_div) * nint; - cpu_pll /= (1 << out_div); - - // DDR PLL from SRIF? - pll = ar7240_reg_rd(DPLL2_ADDRESS_44); - - if (pll & (1 << 30)) { - - out_div = (pll >> 13) & 0x7; - pll = ar7240_reg_rd(0x18116240); - nint = (pll >> 18) & 0x1ff; - //nfrac = pll & 0x0003ffff; - ref_div = (pll >> 27) & 0x1f; - //frac = 1 << 18; - - } else { - // only for tests - // TODO: fix me - *cpu_freq = 560000000; - *ddr_freq = 400000000; - *ahb_freq = 200000000; - return; - } - - ddr_pll = (ref_rate / ref_div) * nint; - ddr_pll /= (1 << out_div); - - clk_ctrl = ar7240_reg_rd(AR934X_CPU_DDR_CLOCK_CONTROL); - - postdiv = (clk_ctrl >> 5) & 0x1f; - - // CPU CLK - if(clk_ctrl & (1 << 2)){ // CPU_PLL_BYPASS - *cpu_freq = ref_rate; - } else if(clk_ctrl & (1 << 20)){ // CPU CLK is derived from CPU_PLL - *cpu_freq = cpu_pll / (postdiv + 1); - } else { // CPU CLK is derived from DDR_PLL - *cpu_freq = ddr_pll / (postdiv + 1); - } - - postdiv = (clk_ctrl >> 10) & 0x1f; - - // DDR CLK - if(clk_ctrl & (1 << 3)){ // DDR_PLL_BYPASS - *ddr_freq = ref_rate; - } else if(clk_ctrl & (1 << 21)){ // DDR CLK is derived from DDR_PLL - *ddr_freq = ddr_pll / (postdiv + 1); - } else { // DDR CLK is derived from CPU_PLL - *ddr_freq = cpu_pll / (postdiv + 1); - } - - postdiv = (clk_ctrl >> 15) & 0x1f; - - // AHB CLK - if(clk_ctrl & (1 << 4)){ // AHB_PLL_BYPASS - *ahb_freq = ref_rate; - } else if(clk_ctrl & (1 << 24)){ // AHB CLK is derived from DDR_PLL - *ahb_freq = ddr_pll / (postdiv + 1); - } else { // AHB CLK is derived from CPU_PLL - *ahb_freq = cpu_pll / (postdiv + 1); - } - -#else - u32 pll, pll_div, ref_div, ahb_div, ddr_div, freq; - - pll = ar7240_reg_rd(AR7240_CPU_PLL_CONFIG); - - pll_div = ((pll & PLL_CONFIG_PLL_DIV_MASK) >> PLL_CONFIG_PLL_DIV_SHIFT); - ref_div = ((pll & PLL_CONFIG_PLL_REF_DIV_MASK) >> PLL_CONFIG_PLL_REF_DIV_SHIFT); - ddr_div = ((pll & PLL_CONFIG_DDR_DIV_MASK) >> PLL_CONFIG_DDR_DIV_SHIFT) + 1; - ahb_div = (((pll & PLL_CONFIG_AHB_DIV_MASK) >> PLL_CONFIG_AHB_DIV_SHIFT) + 1) * 2; - - freq = pll_div * ref_div * 5000000; - - if(cpu_freq){ - *cpu_freq = freq; - } - - if(ddr_freq){ - *ddr_freq = freq/ddr_div; - } - - if(ahb_freq){ - *ahb_freq = freq/ahb_div; - } -#endif -} - -int serial_init(void){ - u32 div, val; -#ifdef CONFIG_WASP - val = ar7240_reg_rd(WASP_BOOTSTRAP_REG); - - if((val & WASP_REF_CLK_25) == 0){ - div = DIV_ROUND_CLOSEST((25 * 1000000), (16 * CONFIG_BAUDRATE)); - } else { - div = DIV_ROUND_CLOSEST((40 * 1000000), (16 * CONFIG_BAUDRATE)); - } -#else - u32 ahb_freq, ddr_freq, cpu_freq; - - ar7240_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq); - - div = DIV_ROUND_CLOSEST(ahb_freq, (16 * CONFIG_BAUDRATE)); - - MY_WRITE(0xb8040000, 0xcff); - MY_WRITE(0xb8040008, 0x3b); - - val = ar7240_reg_rd(0xb8040028); - MY_WRITE(0xb8040028,(val | 0x8002)); - - MY_WRITE(0xb8040008, 0x2f); -#endif - - /* - * set DIAB bit - */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - UART16550_WRITE(OFS_DIVISOR_LSB, (div & 0xff)); - UART16550_WRITE(OFS_DIVISOR_MSB, ((div >> 8) & 0xff)); - - /* clear DIAB bit*/ - UART16550_WRITE(OFS_LINE_CONTROL, 0x00); - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, 0x3); - - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - return(0); -} - -int serial_tstc(void){ - return(UART16550_READ(OFS_LINE_STATUS) & 0x1); -} - -u8 serial_getc(void){ - while(!serial_tstc()); - return(UART16550_READ(OFS_RCV_BUFFER)); -} - -void serial_putc(u8 byte){ - if(byte == '\n'){ - serial_putc('\r'); - } - - while(((UART16550_READ(OFS_LINE_STATUS)) & 0x20) == 0x0); - - UART16550_WRITE(OFS_SEND_BUFFER, byte); -} - -void serial_puts(const char *s){ - while(*s){ - serial_putc(*s++); - } -} diff --git a/u-boot/cpu/mips/ar7240/ar933x_clocks.c b/u-boot/cpu/mips/ar7240/ar933x_clocks.c deleted file mode 100644 index fd01789..0000000 --- a/u-boot/cpu/mips/ar7240/ar933x_clocks.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Atheros AR933x clocks helper functions - * - * Copyright (C) 2014 Piotr Dymacz - * Copyright (C) 2014 Mantas Pucka - * - * SPDX-License-Identifier:GPL-2.0 - */ - -#include -#include -#include -#include -#include - -inline int ar933x_40MHz_xtal(void) -{ - return (ar933x_reg_read(BOOTSTRAP_STATUS_REG) & BOOTSTRAP_SEL_25_40M_MASK); -} - -/* - * Get CPU, RAM and AHB clocks - * Based on: Linux/arch/mips/ath79/clock.c - */ -void ar933x_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq) -{ - u32 ref_rate, clock_ctrl, cpu_config, pll, temp; - - if(ar933x_40MHz_xtal() == 1){ - ref_rate = 40000000; - } else { - ref_rate = 25000000; - } - - /* - * Read CPU CLock Control Register (CLOCK_CONTROL) value - */ - clock_ctrl = ar933x_reg_read(CPU_CLOCK_CONTROL_REG); - - if(clock_ctrl & CPU_CLOCK_CONTROL_BYPASS_MASK){ - /* PLL is bypassed, so all clocks are == reference clock */ - *cpu_freq = ref_rate; - *ddr_freq = ref_rate; - *ahb_freq = ref_rate; - } else { - /* read CPU PLL Configuration register (CPU_PLL_CONFIG) value */ - cpu_config = ar933x_reg_read(CPU_PLL_CONFIG_REG); - - /* REFDIV */ - temp = (cpu_config & CPU_PLL_CONFIG_REFDIV_MASK) - >> CPU_PLL_CONFIG_REFDIV_SHIFT; - pll = ref_rate / temp; - - /* DIV_INT (multiplier) */ - temp = (cpu_config & CPU_PLL_CONFIG_DIV_INT_MASK) - >> CPU_PLL_CONFIG_DIV_INT_SHIFT; - pll *= temp; - - /* OUTDIV */ - temp = (cpu_config & CPU_PLL_CONFIG_OUTDIV_MASK) - >> CPU_PLL_CONFIG_OUTDIV_SHIFT; - - /* Value 0 is not allowed */ - if(temp == 0){ - temp = 1; - } - - pll >>= temp; - - /* CPU clock divider */ - temp = ((clock_ctrl & CPU_CLOCK_CONTROL_CPU_POST_DIV_MASK) - >> CPU_CLOCK_CONTROL_CPU_POST_DIV_SHIFT) + 1; - *cpu_freq = pll / temp; - - /* DDR clock divider */ - temp = ((clock_ctrl & CPU_CLOCK_CONTROL_DDR_POST_DIV_MASK) - >> CPU_CLOCK_CONTROL_DDR_POST_DIV_SHIFT) + 1; - *ddr_freq = pll / temp; - - /* AHB clock divider */ - temp = ((clock_ctrl & CPU_CLOCK_CONTROL_AHB_POST_DIV_MASK) - >> CPU_CLOCK_CONTROL_AHB_POST_DIV_SHIFT) + 1; - *ahb_freq = pll / temp; - } -} diff --git a/u-boot/cpu/mips/ar7240/ar933x_serial.c b/u-boot/cpu/mips/ar7240/ar933x_serial.c deleted file mode 100644 index c6af3db..0000000 --- a/u-boot/cpu/mips/ar7240/ar933x_serial.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * Atheros AR933x UART driver - * - * Copyright (C) 2014 Piotr Dymacz - * Copyright (C) 2008-2010 Atheros Communications Inc. - * - * Values for UART_SCALE and UART_STEP: - * https://www.mail-archive.com/openwrt-devel@lists.openwrt.org/msg22371.html - * - * SPDX-License-Identifier:GPL-2.0 - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static void ar933x_serial_get_scale_step(u32 *uart_scale, u32 *uart_step) -{ - if(ar933x_40MHz_xtal() == 1){ - switch(gd->baudrate){ - case 600: - *uart_scale = 255; - *uart_step = 503; - break; - case 1200: - *uart_scale = 249; - *uart_step = 983; - break; - case 2400: - *uart_scale = 167; - *uart_step = 1321; - break; - case 4800: - *uart_scale = 87; - *uart_step = 1384; - break; - case 9600: - *uart_scale = 45; - *uart_step = 1447; - break; - case 14400: - *uart_scale = 53; - *uart_step = 2548; - break; - case 19200: - *uart_scale = 22; - *uart_step = 1447; - break; - case 28800: - *uart_scale = 26; - *uart_step = 2548; - break; - case 38400: - *uart_scale = 28; - *uart_step = 3649; - break; - case 56000: - *uart_scale = 7; - *uart_step = 1468; - break; - case 57600: - *uart_scale = 34; - *uart_step = 6606; - break; - case 115200: - *uart_scale = 28; - *uart_step = 10947; - break; - case 128000: - *uart_scale = 6; - *uart_step = 2936; - break; - case 153600: - *uart_scale = 18; - *uart_step = 9563; - break; - case 230400: - *uart_scale = 16; - *uart_step = 12834; - break; - case 250000: - *uart_scale = 4; - *uart_step = 4096; - break; - case 256000: - *uart_scale = 6; - *uart_step = 5872; - break; - case 460800: - *uart_scale = 7; - *uart_step = 12079; - break; - case 576000: - *uart_scale = 4; - *uart_step = 9437; - break; - case 921600: - *uart_scale = 3; - *uart_step = 12079; - break; - case 1000000: - *uart_scale = 2; - *uart_step = 9830; - break; - case 1152000: - *uart_scale = 2; - *uart_step = 11324; - break; - case 1500000: - *uart_scale = 0; - *uart_step = 4915; - break; - case 2000000: - *uart_scale = 0; - *uart_step = 6553; - break; - default: - *uart_scale = (40000000 / (16 * gd->baudrate)) - 1; - *uart_step = 8192; - } - } else { - switch(gd->baudrate){ - case 600: - *uart_scale = 255; - *uart_step = 805; - break; - case 1200: - *uart_scale = 209; - *uart_step = 1321; - break; - case 2400: - *uart_scale = 104; - *uart_step = 1321; - break; - case 4800: - *uart_scale = 54; - *uart_step = 1384; - break; - case 9600: - *uart_scale = 78; - *uart_step = 3976; - break; - case 14400: - *uart_scale = 98; - *uart_step = 7474; - break; - case 19200: - *uart_scale = 55; - *uart_step = 5637; - break; - case 28800: - *uart_scale = 77; - *uart_step = 11777; - break; - case 38400: - *uart_scale = 36; - *uart_step = 7449; - break; - case 56000: - *uart_scale = 4; - *uart_step = 1468; - break; - case 57600: - *uart_scale = 35; - *uart_step = 10871; - break; - case 115200: - *uart_scale = 20; - *uart_step = 12683; - break; - case 128000: - *uart_scale = 11; - *uart_step = 8053; - break; - case 153600: - *uart_scale = 9; - *uart_step = 8053; - break; - case 230400: - *uart_scale = 9; - *uart_step = 12079; - break; - case 250000: - *uart_scale = 6; - *uart_step = 9175; - break; - case 256000: - *uart_scale = 5; - *uart_step = 8053; - break; - case 460800: - *uart_scale = 4; - *uart_step = 12079; - break; - case 576000: - *uart_scale = 3; - *uart_step = 12079; - break; - case 921600: - *uart_scale = 1; - *uart_step = 9663; - break; - case 1000000: - *uart_scale = 1; - *uart_step = 10485; - break; - case 1152000: - *uart_scale = 1; - *uart_step = 12079; - break; - case 1500000: - *uart_scale = 0; - *uart_step = 7864; - break; - case 2000000: - *uart_scale = 0; - *uart_step = 10485; - break; - default: - *uart_scale = (25000000 / (16 * gd->baudrate)) - 1; - *uart_step = 8192; - } - } -} - -void serial_setbrg(void) -{ - /* TODO: better clock calculation, baudrate, etc. */ - u32 uart_clock; - u32 uart_scale; - u32 uart_step; - - ar933x_serial_get_scale_step(&uart_scale, &uart_step); - - uart_clock = (uart_scale << UART_CLOCK_SCALE_SHIFT); - uart_clock |= (uart_step << UART_CLOCK_STEP_SHIFT); - - ar933x_reg_write(UART_CLOCK_REG, uart_clock); -} - -int serial_init(void) -{ - u32 uart_cs; - - /* - * Set GPIO10 (UART_SO) as output and enable UART, - * BIT(15) in GPIO_FUNCTION_1 register must be written with 1 - */ - ar933x_reg_read_set(GPIO_OE_REG, GPIO10); - - ar933x_reg_read_set(GPIO_FUNCTION_1_REG, - (1 << GPIO_FUNCTION_1_UART_EN_SHIFT) | - (1 << 15)); - - /* - * UART controller configuration: - * - no DMA - * - no interrupt - * - DCE mode - * - no flow control - * - set RX ready oride - * - set TX ready oride - */ - uart_cs = (0 << UART_CS_DMA_EN_SHIFT) | - (0 << UART_CS_HOST_INT_EN_SHIFT) | - (1 << UART_CS_RX_READY_ORIDE_SHIFT) | - (1 << UART_CS_TX_READY_ORIDE_SHIFT) | - (UART_CS_IFACE_MODE_DCE_VAL << UART_CS_IFACE_MODE_SHIFT) | - (UART_CS_FLOW_MODE_NO_VAL << UART_CS_FLOW_MODE_SHIFT); - - ar933x_reg_write(UART_CS_REG, uart_cs); - - serial_setbrg(); - - return 0; -} - -void serial_putc(const char c) -{ - u32 uart_data; - - if(c == '\n') - serial_putc('\r'); - - /* Wait for FIFO */ - do{ - uart_data = ar933x_reg_read(UART_DATA_REG); - } while(((uart_data & UART_TX_CSR_MASK) >> UART_TX_CSR_SHIFT) == 0); - - /* Put data in buffer and set CSR bit */ - uart_data = (u32)c | (1 << UART_TX_CSR_SHIFT); - - ar933x_reg_write(UART_DATA_REG, uart_data); -} - -int serial_getc(void) -{ - u32 uart_data; - - while(!serial_tstc()) - ; - - uart_data = ar933x_reg_read(UART_DATA_REG); - - ar933x_reg_write(UART_DATA_REG, (1 << UART_RX_CSR_SHIFT)); - - return (uart_data & UART_TX_RX_DATA_MASK); -} - -int serial_tstc(void) -{ - u32 uart_data = ar933x_reg_read(UART_DATA_REG); - - if((uart_data & UART_RX_CSR_MASK) >> UART_RX_CSR_SHIFT){ - return 1; - } - - return 0; -} - -void serial_puts(const char *s) -{ - while(*s){ - serial_putc(*s++); - } -}