From: Felix Fietkau Date: Sun, 18 Jan 2015 20:17:07 +0000 (+0000) Subject: ralink: use fe_reset to control all reset X-Git-Tag: reboot~4630 X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=03ea0cf6f18593a587d240d56b473345c035db98;p=oweals%2Fopenwrt.git ralink: use fe_reset to control all reset Signed-off-by: michael lee SVN-Revision: 44044 --- diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c index 247983b79e..55d5729f43 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c @@ -192,7 +192,6 @@ #define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x)) #define RT5350_EWS_REG_LED_POLARITY 0x168 #define RT5350_RESET_EPHY BIT(24) -#define SYSC_REG_RESET_CTRL 0x34 enum { /* Global attributes. */ @@ -512,9 +511,7 @@ static void esw_hw_init(struct rt305x_esw *esw) if (ralink_soc == RT305X_SOC_RT3352) { /* reset EPHY */ - u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL); - rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL); - rt_sysc_w32(val, SYSC_REG_RESET_CTRL); + fe_reset(RT5350_RESET_EPHY); rt305x_mii_write(esw, 0, 31, 0x8000); for (i = 0; i < 5; i++) { @@ -563,9 +560,7 @@ static void esw_hw_init(struct rt305x_esw *esw) rt305x_mii_write(esw, 0, 31, 0x8000); } else if (ralink_soc == RT305X_SOC_RT5350) { /* reset EPHY */ - u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL); - rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL); - rt_sysc_w32(val, SYSC_REG_RESET_CTRL); + fe_reset(RT5350_RESET_EPHY); /* set the led polarity */ esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY); @@ -622,9 +617,7 @@ static void esw_hw_init(struct rt305x_esw *esw) u32 val; /* reset EPHY */ - val = rt_sysc_r32(SYSC_REG_RESET_CTRL); - rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL); - rt_sysc_w32(val, SYSC_REG_RESET_CTRL); + fe_reset(RT5350_RESET_EPHY); rt305x_mii_write(esw, 0, 31, 0x2000); /* change G2 page */ rt305x_mii_write(esw, 0, 26, 0x0020); diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c index df85929d6d..803970487a 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c @@ -80,7 +80,6 @@ #define SYSC_REG_CHIP_REV_ID 0x0c #define SYSC_REG_CFG1 0x14 -#define SYSC_REG_RESET_CTRL 0x34 #define RST_CTRL_MCM BIT(2) #define SYSC_PAD_RGMII2_MDIO 0x58 #define SYSC_GPIO_MODE 0x60 @@ -576,10 +575,7 @@ static void gsw_hw_init_mt7621(struct mt7620_gsw *gsw, struct device_node *np) u32 val; /* Hardware reset Switch */ - val = rt_sysc_r32(SYSC_REG_RESET_CTRL); - rt_sysc_w32(val | RST_CTRL_MCM, SYSC_REG_RESET_CTRL); - udelay(1000); - rt_sysc_w32(val, SYSC_REG_RESET_CTRL); + fe_reset(RST_CTRL_MCM); udelay(10000); /* reduce RGMII2 PAD driving strength */ diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.c index 4252ff3ad2..28650bbceb 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.c @@ -60,6 +60,8 @@ #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1)) #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1)) +#define SYSC_REG_RSTCTRL 0x34 + static int fe_msg_level = -1; module_param_named(msg_level, fe_msg_level, int, 0); MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); @@ -112,6 +114,20 @@ u32 fe_reg_r32(enum fe_reg reg) return fe_r32(fe_reg_table[reg]); } +void fe_reset(u32 reset_bits) +{ + u32 t; + + t = rt_sysc_r32(SYSC_REG_RSTCTRL); + t |= reset_bits; + rt_sysc_w32(t , SYSC_REG_RSTCTRL); + udelay(10); + + t &= ~reset_bits; + rt_sysc_w32(t, SYSC_REG_RSTCTRL); + udelay(10); +} + static inline void fe_int_disable(u32 mask) { fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask, diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.h b/target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.h index 007ad722d6..b875de9fd4 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.h +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.h @@ -474,6 +474,8 @@ void fe_fwd_config(struct fe_priv *priv); void fe_reg_w32(u32 val, enum fe_reg reg); u32 fe_reg_r32(enum fe_reg reg); +void fe_reset(u32 reset_bits); + static inline void *priv_netdev(struct fe_priv *priv) { return (char *)priv - ALIGN(sizeof(struct net_device), NETDEV_ALIGN); diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c index 0c1384b51c..6123f24778 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c @@ -39,8 +39,6 @@ #define MT7621_TX_DMA_UDF BIT(19) #define TX_DMA_FP_BMAP ((0xff) << 19) -#define SYSC_REG_RESET_CTRL 0x34 - #define CDMA_ICS_EN BIT(2) #define CDMA_UCS_EN BIT(1) #define CDMA_TCS_EN BIT(0) @@ -105,18 +103,12 @@ static const u32 mt7621_reg_table[FE_REG_COUNT] = { static void mt7620_fe_reset(void) { - u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL); - - rt_sysc_w32(val | MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL); - rt_sysc_w32(val, SYSC_REG_RESET_CTRL); + fe_reset(MT7620A_RESET_FE | MT7620A_RESET_ESW); } static void mt7621_fe_reset(void) { - u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL); - - rt_sysc_w32(val | MT7621_RESET_FE, SYSC_REG_RESET_CTRL); - rt_sysc_w32(val, SYSC_REG_RESET_CTRL); + fe_reset(MT7621_RESET_FE); } static void mt7620_rxcsum_config(bool enable) diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt2880.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt2880.c index 4602745542..43467310bd 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt2880.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt2880.c @@ -22,7 +22,6 @@ #include "ralink_soc_eth.h" #include "mdio_rt2880.h" -#define SYSC_REG_RESET_CTRL 0x034 #define RT2880_RESET_FE BIT(18) static void rt2880_init_data(struct fe_soc_data *data, @@ -39,7 +38,7 @@ static void rt2880_init_data(struct fe_soc_data *data, void rt2880_fe_reset(void) { - rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL); + fe_reset(RT2880_RESET_FE); } static int rt2880_fwd_config(struct fe_priv *priv) diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt305x.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt305x.c index 348005b345..8f7be46889 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt305x.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt305x.c @@ -24,7 +24,6 @@ #define RT305X_RESET_FE BIT(21) #define RT305X_RESET_ESW BIT(23) -#define SYSC_REG_RESET_CTRL 0x034 static const u32 rt5350_reg_table[FE_REG_COUNT] = { [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG, @@ -74,8 +73,7 @@ static int rt3050_fwd_config(struct fe_priv *priv) static void rt305x_fe_reset(void) { - rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL); - rt_sysc_w32(0, SYSC_REG_RESET_CTRL); + fe_reset(RT305X_RESET_FE); } static void rt5350_init_data(struct fe_soc_data *data, @@ -123,8 +121,7 @@ static void rt5350_tx_dma(struct fe_tx_dma *txd) static void rt5350_fe_reset(void) { - rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL); - rt_sysc_w32(0, SYSC_REG_RESET_CTRL); + fe_reset(RT305X_RESET_FE | RT305X_RESET_ESW); } static struct fe_soc_data rt3050_data = { diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt3883.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt3883.c index 1393f02929..71cb74759e 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt3883.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt3883.c @@ -22,19 +22,11 @@ #include "ralink_soc_eth.h" #include "mdio_rt2880.h" -#define RT3883_SYSC_REG_RSTCTRL 0x34 #define RT3883_RSTCTRL_FE BIT(21) static void rt3883_fe_reset(void) { - u32 t; - - t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); - t |= RT3883_RSTCTRL_FE; - rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL); - - t &= ~RT3883_RSTCTRL_FE; - rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL); + fe_reset(RT3883_RSTCTRL_FE); } static int rt3883_fwd_config(struct fe_priv *priv)