Merge branch 'master' of git://git.denx.de/u-boot-usb
authorTom Rini <trini@konsulko.com>
Mon, 6 Jun 2016 14:04:58 +0000 (10:04 -0400)
committerTom Rini <trini@konsulko.com>
Mon, 6 Jun 2016 17:37:56 +0000 (13:37 -0400)
Modified:
configs/ls1012afrdm_qspi_defconfig
configs/ls1012aqds_qspi_defconfig
configs/ls1012ardb_qspi_defconfig
include/configs/ls1012afrdm.h
include/configs/ls1012aqds.h
include/configs/ls1012ardb.h

Signed-off-by: Tom Rini <trini@konsulko.com>
12 files changed:
1  2 
configs/ls1012afrdm_qspi_defconfig
configs/ls1012aqds_qspi_defconfig
configs/ls1012ardb_qspi_defconfig
configs/xilinx_zynqmp_ep_defconfig
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
configs/xilinx_zynqmp_zcu102_defconfig
configs/xilinx_zynqmp_zcu102_revB_defconfig
include/configs/ls1012afrdm.h
include/configs/ls1012aqds.h
include/configs/ls1012ardb.h
include/configs/xilinx_zynqmp.h

index 349758b84c9da71fb7aba4191acd3e67a1ea8db9,0000000000000000000000000000000000000000..04189debcf191beb1e13dafb020a9f49c2fbed68
mode 100644,000000..100644
--- /dev/null
@@@ -1,29 -1,0 +1,32 @@@
 +CONFIG_ARM=y
 +CONFIG_TARGET_LS1012AFRDM=y
 +# CONFIG_SYS_MALLOC_F is not set
 +CONFIG_SPI_FLASH=y
 +CONFIG_DM_SPI=y
 +CONFIG_DM_SPI_FLASH=y
 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
 +CONFIG_FIT=y
 +CONFIG_FIT_VERBOSE=y
 +CONFIG_OF_BOARD_SETUP=y
 +CONFIG_OF_STDOUT_VIA_ALIAS=y
 +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
 +CONFIG_HUSH_PARSER=y
 +CONFIG_CMD_GREPENV=y
 +CONFIG_CMD_SF=y
 +CONFIG_CMD_I2C=y
 +CONFIG_CMD_USB=y
 +# CONFIG_CMD_SETEXPR is not set
 +CONFIG_CMD_DHCP=y
 +CONFIG_CMD_MII=y
 +CONFIG_CMD_PING=y
 +CONFIG_CMD_CACHE=y
 +CONFIG_CMD_EXT2=y
 +CONFIG_CMD_FAT=y
 +CONFIG_OF_CONTROL=y
 +CONFIG_NET_RANDOM_ETHADDR=y
 +CONFIG_DM=y
 +CONFIG_NETDEVICES=y
 +CONFIG_SYS_NS16550=y
++CONFIG_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_DWC3=y
index 2bc178c761b929e4bcd9016f5b6817a429419b1b,0000000000000000000000000000000000000000..935f2fdaa50e53df333d99facf3ab20edb2ab773
mode 100644,000000..100644
--- /dev/null
@@@ -1,32 -1,0 +1,35 @@@
 +CONFIG_ARM=y
 +CONFIG_TARGET_LS1012AQDS=y
 +# CONFIG_SYS_MALLOC_F is not set
 +CONFIG_SPI_FLASH=y
 +CONFIG_DM_SPI=y
 +CONFIG_DM_SPI_FLASH=y
 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
 +CONFIG_FIT=y
 +CONFIG_FIT_VERBOSE=y
 +CONFIG_OF_BOARD_SETUP=y
 +CONFIG_OF_STDOUT_VIA_ALIAS=y
 +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
 +CONFIG_HUSH_PARSER=y
 +CONFIG_CMD_GREPENV=y
 +CONFIG_CMD_MMC=y
 +CONFIG_CMD_SF=y
 +CONFIG_CMD_I2C=y
 +CONFIG_CMD_USB=y
 +# CONFIG_CMD_SETEXPR is not set
 +CONFIG_CMD_DHCP=y
 +CONFIG_CMD_MII=y
 +CONFIG_CMD_PING=y
 +CONFIG_CMD_CACHE=y
 +CONFIG_CMD_EXT2=y
 +CONFIG_CMD_FAT=y
 +CONFIG_OF_CONTROL=y
 +CONFIG_NET_RANDOM_ETHADDR=y
 +CONFIG_DM=y
 +CONFIG_NETDEVICES=y
 +CONFIG_E1000=y
 +CONFIG_SYS_NS16550=y
 +CONFIG_FSL_DSPI=y
++CONFIG_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_DWC3=y
index 456eebd1592cd9a5686926344e5e7b6dc97f4ff6,0000000000000000000000000000000000000000..5c28bd10715c3854fad70ba77145981d77fe254a
mode 100644,000000..100644
--- /dev/null
@@@ -1,32 -1,0 +1,35 @@@
 +CONFIG_ARM=y
 +CONFIG_TARGET_LS1012ARDB=y
 +# CONFIG_SYS_MALLOC_F is not set
 +CONFIG_SPI_FLASH=y
 +CONFIG_DM_SPI=y
 +CONFIG_DM_SPI_FLASH=y
 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
 +CONFIG_FIT=y
 +CONFIG_FIT_VERBOSE=y
 +CONFIG_OF_BOARD_SETUP=y
 +CONFIG_OF_STDOUT_VIA_ALIAS=y
 +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
 +CONFIG_HUSH_PARSER=y
 +CONFIG_CMD_GREPENV=y
 +CONFIG_CMD_MMC=y
 +CONFIG_CMD_SF=y
 +CONFIG_CMD_I2C=y
 +CONFIG_CMD_USB=y
 +# CONFIG_CMD_SETEXPR is not set
 +CONFIG_CMD_DHCP=y
 +CONFIG_CMD_MII=y
 +CONFIG_CMD_PING=y
 +CONFIG_CMD_CACHE=y
 +CONFIG_CMD_EXT2=y
 +CONFIG_CMD_FAT=y
 +CONFIG_OF_CONTROL=y
 +CONFIG_NET_RANDOM_ETHADDR=y
 +CONFIG_DM=y
 +CONFIG_NETDEVICES=y
 +CONFIG_E1000=y
 +CONFIG_SYS_NS16550=y
 +CONFIG_FSL_DSPI=y
++CONFIG_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_DWC3=y
Simple merge
index ffbedfa2ef7f3b86c1ed48b0ecece04f872e66db,3aa80cbe9782dd23e710cf900a36ee37db18e437..cc13179a1e5fa77cea165490234415171478f1af
@@@ -43,12 -40,9 +43,14 @@@ CONFIG_SPI_FLASH_BAR=
  CONFIG_SPI_FLASH_SST=y
  CONFIG_DM_ETH=y
  CONFIG_ZYNQ_GEM=y
 +CONFIG_DEBUG_UART=y
 +CONFIG_DEBUG_UART_ZYNQ=y
 +CONFIG_DEBUG_UART_BASE=0xff000000
 +CONFIG_DEBUG_UART_CLOCK=100000000
 +CONFIG_DEBUG_UART_ANNOUNCE=y
  CONFIG_USB=y
+ CONFIG_USB_XHCI_HCD=y
+ CONFIG_USB_XHCI_DWC3=y
  CONFIG_USB_DWC3=y
  CONFIG_USB_DWC3_GADGET=y
  CONFIG_USB_ULPI_VIEWPORT=y
index 3e7c430c6461ead5e6e2b058c20d596d0a3cece3,0000000000000000000000000000000000000000..ad81142dcd49d540f7d02e32d6a2700be3015315
mode 100644,000000..100644
--- /dev/null
@@@ -1,44 -1,0 +1,42 @@@
- #define CONFIG_USB_XHCI
 +/*
 + * Copyright 2016 Freescale Semiconductor, Inc.
 + *
 + * SPDX-License-Identifier:   GPL-2.0+
 + */
 +
 +#ifndef __LS1012ARDB_H__
 +#define __LS1012ARDB_H__
 +
 +#include "ls1012a_common.h"
 +
 +#define CONFIG_DIMM_SLOTS_PER_CTLR    1
 +#define CONFIG_CHIP_SELECTS_PER_CTRL  1
 +#define CONFIG_NR_DRAM_BANKS          2
 +#define CONFIG_SYS_SDRAM_SIZE         0x20000000
 +
 +#define CONFIG_SYS_MMDC_CORE_CONTROL_1                0x04180000
 +#define CONFIG_SYS_MMDC_CORE_CONTROL_2                0x84180000
 +
 +#define CONFIG_CMD_MEMINFO
 +#define CONFIG_CMD_MEMTEST
 +#define CONFIG_SYS_MEMTEST_START      0x80000000
 +#define CONFIG_SYS_MEMTEST_END                0x9fffffff
 +
 +/*
 +* USB
 +*/
 +#define CONFIG_HAS_FSL_XHCI_USB
 +
 +#ifdef CONFIG_HAS_FSL_XHCI_USB
- #define CONFIG_USB_XHCI_DWC3
 +#define CONFIG_USB_XHCI_FSL
 +#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 +#define CONFIG_USB_STORAGE
 +#endif
 +
 +#define CONFIG_CMD_MEMINFO
 +#define CONFIG_CMD_MEMTEST
 +#define CONFIG_SYS_MEMTEST_START      0x80000000
 +#define CONFIG_SYS_MEMTEST_END                0x9fffffff
 +
 +#endif /* __LS1012ARDB_H__ */
index 2d84095e94a6858cbe55f59b3ec5cfd04cc9319d,0000000000000000000000000000000000000000..fcf402c836ecd3ba027d094a459fc767dd2729a8
mode 100644,000000..100644
--- /dev/null
@@@ -1,191 -1,0 +1,189 @@@
- #define CONFIG_USB_XHCI
 +/*
 + * Copyright 2016 Freescale Semiconductor, Inc.
 + *
 + * SPDX-License-Identifier:   GPL-2.0+
 + */
 +
 +#ifndef __LS1012AQDS_H__
 +#define __LS1012AQDS_H__
 +
 +#include "ls1012a_common.h"
 +
 +
 +#define CONFIG_DIMM_SLOTS_PER_CTLR    1
 +#define CONFIG_CHIP_SELECTS_PER_CTRL  1
 +#define CONFIG_NR_DRAM_BANKS          2
 +#define CONFIG_SYS_SDRAM_SIZE         0x40000000
 +
 +#define CONFIG_SYS_MMDC_CORE_CONTROL_1                0x05180000
 +#define CONFIG_SYS_MMDC_CORE_CONTROL_2                0x85180000
 +
 +/*
 + * QIXIS Definitions
 + */
 +#define CONFIG_FSL_QIXIS
 +
 +#ifdef CONFIG_FSL_QIXIS
 +#define CONFIG_QIXIS_I2C_ACCESS
 +#define CONFIG_SYS_I2C_FPGA_ADDR      0x66
 +#define QIXIS_LBMAP_BRDCFG_REG                0x04
 +#define QIXIS_LBMAP_SWITCH            6
 +#define QIXIS_LBMAP_MASK              0xf7
 +#define QIXIS_LBMAP_SHIFT             0
 +#define QIXIS_LBMAP_DFLTBANK          0x00
 +#define QIXIS_LBMAP_ALTBANK           0x08
 +#define QIXIS_RST_CTL_RESET           0x41
 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE  0x20
 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
 +#endif
 +
 +/*
 + * I2C bus multiplexer
 + */
 +#define I2C_MUX_PCA_ADDR_PRI          0x77
 +#define I2C_MUX_PCA_ADDR_SEC          0x76 /* Secondary multiplexer */
 +#define I2C_RETIMER_ADDR              0x18
 +#define I2C_MUX_CH_DEFAULT            0x8
 +#define I2C_MUX_CH_CH7301             0xC
 +#define I2C_MUX_CH5                   0xD
 +#define I2C_MUX_CH7                   0xF
 +
 +#define I2C_MUX_CH_VOL_MONITOR 0xa
 +
 +/*
 +* RTC configuration
 +*/
 +#define RTC
 +#define CONFIG_RTC_PCF8563 1
 +#define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 +#define CONFIG_CMD_DATE
 +
 +/* EEPROM */
 +#define CONFIG_ID_EEPROM
 +#define CONFIG_CMD_EEPROM
 +#define CONFIG_SYS_I2C_EEPROM_NXID
 +#define CONFIG_SYS_EEPROM_BUS_NUM    0
 +#define CONFIG_SYS_I2C_EEPROM_ADDR   0x57
 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN     1
 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 +
 +
 +/* Voltage monitor on channel 2*/
 +#define I2C_VOL_MONITOR_ADDR           0x40
 +#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 +#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 +#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 +
 +/* DSPI */
 +#define CONFIG_FSL_DSPI1
 +#define CONFIG_DEFAULT_SPI_BUS 1
 +
 +#define CONFIG_CMD_SPI
 +#define MMAP_DSPI          DSPI1_BASE_ADDR
 +
 +#define CONFIG_SYS_DSPI_CTAR0   1
 +
 +#define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
 +                              DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
 +                              DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
 +                              DSPI_CTAR_DT(0))
 +#define CONFIG_SPI_FLASH_SST /* cs1 */
 +
 +#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
 +                              DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
 +                              DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
 +                              DSPI_CTAR_DT(0))
 +#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
 +
 +#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
 +                              DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
 +                              DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
 +                              DSPI_CTAR_DT(0))
 +#define CONFIG_SPI_FLASH_EON /* cs3 */
 +
 +#define CONFIG_SF_DEFAULT_SPEED      10000000
 +#define CONFIG_SF_DEFAULT_MODE       SPI_MODE_0
 +#define CONFIG_SF_DEFAULT_BUS        1
 +#define CONFIG_SF_DEFAULT_CS         0
 +
 +/*
 +* USB
 +*/
 +/* EHCI Support - disbaled by default */
 +/*#define CONFIG_HAS_FSL_DR_USB*/
 +
 +#ifdef CONFIG_HAS_FSL_DR_USB
 +#define CONFIG_USB_EHCI
 +#define CONFIG_USB_EHCI_FSL
 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 +#endif
 +
 +/*XHCI Support - enabled by default*/
 +#define CONFIG_HAS_FSL_XHCI_USB
 +
 +#ifdef CONFIG_HAS_FSL_XHCI_USB
- #define CONFIG_USB_XHCI_DWC3
 +#define CONFIG_USB_XHCI_FSL
 +#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 +#define CONFIG_USB_STORAGE
 +#endif
 +
 +/*  MMC  */
 +#define CONFIG_MMC
 +#ifdef CONFIG_MMC
 +#define CONFIG_FSL_ESDHC
 +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 +#define CONFIG_GENERIC_MMC
 +#define CONFIG_DOS_PARTITION
 +#endif
 +
 +/* SATA */
 +#define CONFIG_LIBATA
 +#define       CONFIG_SCSI
 +#define CONFIG_SCSI_AHCI
 +#define CONFIG_SCSI_AHCI_PLAT
 +#define CONFIG_CMD_SCSI
 +#define CONFIG_DOS_PARTITION
 +#define CONFIG_BOARD_LATE_INIT
 +
 +#define CONFIG_SYS_SATA                               AHCI_BASE_ADDR
 +
 +#define CONFIG_SYS_SCSI_MAX_SCSI_ID           1
 +#define CONFIG_SYS_SCSI_MAX_LUN                       1
 +#define CONFIG_SYS_SCSI_MAX_DEVICE            (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 +                                              CONFIG_SYS_SCSI_MAX_LUN)
 +#define CONFIG_PCI            /* Enable PCI/PCIE */
 +#define CONFIG_PCIE1          /* PCIE controller 1 */
 +#define CONFIG_PCIE_LAYERSCAPE        /* Use common FSL Layerscape PCIe code */
 +#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
 +
 +#define CONFIG_SYS_PCI_64BIT
 +
 +#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
 +#define CONFIG_SYS_PCIE_CFG0_SIZE     0x00001000      /* 4k */
 +#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
 +#define CONFIG_SYS_PCIE_CFG1_SIZE     0x00001000      /* 4k */
 +
 +#define CONFIG_SYS_PCIE_IO_BUS                0x00000000
 +#define CONFIG_SYS_PCIE_IO_PHYS_OFF   0x00010000
 +#define CONFIG_SYS_PCIE_IO_SIZE               0x00010000      /* 64k */
 +
 +#define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
 +#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
 +#define CONFIG_SYS_PCIE_MEM_SIZE        0x80000000      /* 128M */
 +
 +#define CONFIG_NET_MULTI
 +#define CONFIG_PCI_PNP
 +#define CONFIG_PCI_SCAN_SHOW
 +#define CONFIG_CMD_PCI
 +
 +#define CONFIG_CMD_MEMINFO
 +#define CONFIG_CMD_MEMTEST
 +#define CONFIG_SYS_MEMTEST_START      0x80000000
 +#define CONFIG_SYS_MEMTEST_END                0x9fffffff
 +
 +#define CONFIG_MISC_INIT_R
 +
 +#endif /* __LS1012AQDS_H__ */
index f63c66a8d99c98b2ccb2695fe83f69a3da4d804e,0000000000000000000000000000000000000000..6046ab789525d8bb975aa7d7fea45fca9130d0f3
mode 100644,000000..100644
--- /dev/null
@@@ -1,107 -1,0 +1,105 @@@
- #define CONFIG_USB_XHCI
 +/*
 + * Copyright 2016 Freescale Semiconductor, Inc.
 + *
 + * SPDX-License-Identifier:   GPL-2.0+
 + */
 +
 +#ifndef __LS1012ARDB_H__
 +#define __LS1012ARDB_H__
 +
 +#include "ls1012a_common.h"
 +
 +
 +#define CONFIG_DIMM_SLOTS_PER_CTLR    1
 +#define CONFIG_CHIP_SELECTS_PER_CTRL  1
 +#define CONFIG_NR_DRAM_BANKS          2
 +#define CONFIG_SYS_SDRAM_SIZE         0x40000000
 +
 +#define CONFIG_SYS_MMDC_CORE_CONTROL_1                0x05180000
 +#define CONFIG_SYS_MMDC_CORE_CONTROL_2                0x85180000
 +
 +#define CONFIG_CMD_MEMINFO
 +#define CONFIG_CMD_MEMTEST
 +#define CONFIG_SYS_MEMTEST_START      0x80000000
 +#define CONFIG_SYS_MEMTEST_END                0x9fffffff
 +
 +/*
 +* USB
 +*/
 +#define CONFIG_HAS_FSL_XHCI_USB
 +
 +#ifdef CONFIG_HAS_FSL_XHCI_USB
- #define CONFIG_USB_XHCI_DWC3
 +#define CONFIG_USB_XHCI_FSL
 +#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 +#define CONFIG_USB_STORAGE
 +#endif
 +
 +/*
 + * I2C IO expander
 + */
 +
 +#define I2C_MUX_IO1_ADDR      0x24
 +#define __SW_BOOT_MASK                0xFC
 +#define __SW_BOOT_EMU         0x10
 +#define __SW_BOOT_BANK1               0x00
 +#define __SW_BOOT_BANK2               0x01
 +#define __SW_REV_MASK         0x07
 +#define __SW_REV_A            0xF8
 +#define __SW_REV_B            0xF0
 +
 +/*  MMC  */
 +#define CONFIG_MMC
 +#ifdef CONFIG_MMC
 +#define CONFIG_FSL_ESDHC
 +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 +#define CONFIG_GENERIC_MMC
 +#define CONFIG_DOS_PARTITION
 +#endif
 +
 +/* SATA */
 +#define CONFIG_LIBATA
 +#define       CONFIG_SCSI
 +#define CONFIG_SCSI_AHCI
 +#define CONFIG_SCSI_AHCI_PLAT
 +#define CONFIG_CMD_SCSI
 +#define CONFIG_DOS_PARTITION
 +#define CONFIG_BOARD_LATE_INIT
 +
 +#define CONFIG_SYS_SATA                               AHCI_BASE_ADDR
 +
 +#define CONFIG_SYS_SCSI_MAX_SCSI_ID           1
 +#define CONFIG_SYS_SCSI_MAX_LUN                       1
 +#define CONFIG_SYS_SCSI_MAX_DEVICE            (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 +                                              CONFIG_SYS_SCSI_MAX_LUN)
 +#define CONFIG_PCI            /* Enable PCI/PCIE */
 +#define CONFIG_PCIE1          /* PCIE controller 1 */
 +#define CONFIG_PCIE_LAYERSCAPE        /* Use common FSL Layerscape PCIe code */
 +#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
 +
 +#define CONFIG_SYS_PCI_64BIT
 +
 +#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
 +#define CONFIG_SYS_PCIE_CFG0_SIZE     0x00001000      /* 4k */
 +#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
 +#define CONFIG_SYS_PCIE_CFG1_SIZE     0x00001000      /* 4k */
 +
 +#define CONFIG_SYS_PCIE_IO_BUS                0x00000000
 +#define CONFIG_SYS_PCIE_IO_PHYS_OFF   0x00010000
 +#define CONFIG_SYS_PCIE_IO_SIZE               0x00010000      /* 64k */
 +
 +#define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
 +#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
 +#define CONFIG_SYS_PCIE_MEM_SIZE        0x80000000      /* 128M */
 +
 +#define CONFIG_NET_MULTI
 +#define CONFIG_PCI_PNP
 +#define CONFIG_PCI_SCAN_SHOW
 +#define CONFIG_CMD_PCI
 +
 +#define CONFIG_CMD_MEMINFO
 +#define CONFIG_CMD_MEMTEST
 +#define CONFIG_SYS_MEMTEST_START      0x80000000
 +#define CONFIG_SYS_MEMTEST_END                0x9fffffff
 +
 +#endif /* __LS1012ARDB_H__ */
Simple merge