mxs_nand: Add support for i.MX8M

Update the gpmi/apbh_dma/bch drivers and relevant registers for i.MX8M.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/include/asm/mach-imx/dma.h b/arch/arm/include/asm/mach-imx/dma.h
index ca70731b9ebc1c609b31ceca600bf390b837dcea..cb73aaeeb558b071c210f7b995fafa5c9f4808c9 100644 (file)
--- a/arch/arm/include/asm/mach-imx/dma.h
+++ b/arch/arm/include/asm/mach-imx/dma.h
@@ -53,7 +53,7 @@ enum {
        MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
        MXS_MAX_DMA_CHANNELS,
 };
-#elif defined(CONFIG_MX6) || defined(CONFIG_MX7)
+#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
 enum {
        MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
        MXS_DMA_CHANNEL_AHB_APBH_GPMI1,

diff --git a/arch/arm/include/asm/mach-imx/regs-apbh.h b/arch/arm/include/asm/mach-imx/regs-apbh.h
index d7baf1334342e0ca781ae5309ec22e96b95318c2..d68953efd27a8e68cf5fea5c32df193ec10e9326 100644 (file)
--- a/arch/arm/include/asm/mach-imx/regs-apbh.h
+++ b/arch/arm/include/asm/mach-imx/regs-apbh.h
@@ -95,7 +95,7 @@ struct mxs_apbh_regs {
        mxs_reg_32(hw_apbh_version)
 };
 
-#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
 struct mxs_apbh_regs {
        mxs_reg_32(hw_apbh_ctrl0)
        mxs_reg_32(hw_apbh_ctrl1)
@@ -274,7 +274,7 @@ struct mxs_apbh_regs {
 #define        APBH_CTRL0_CLKGATE_CHANNEL_NAND7                0x0800
 #define        APBH_CTRL0_CLKGATE_CHANNEL_HSADC                0x1000
 #define        APBH_CTRL0_CLKGATE_CHANNEL_LCDIF                0x2000
-#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
 #define        APBH_CTRL0_CLKGATE_CHANNEL_OFFSET               0
 #define        APBH_CTRL0_CLKGATE_CHANNEL_NAND0                0x0001
 #define        APBH_CTRL0_CLKGATE_CHANNEL_NAND1                0x0002
@@ -390,7 +390,7 @@ struct mxs_apbh_regs {
 #define        APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF          0x2000
 #endif
 
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
 #define        APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET          16
 #endif
 

diff --git a/arch/arm/include/asm/mach-imx/regs-bch.h b/arch/arm/include/asm/mach-imx/regs-bch.h
index 3c1abb7221c8cbb0d33f618ea24a006110d1880a..4b99edbb3df7d3702159f5ebd66478789e5cb3fe 100644 (file)
--- a/arch/arm/include/asm/mach-imx/regs-bch.h
+++ b/arch/arm/include/asm/mach-imx/regs-bch.h
@@ -127,7 +127,7 @@ struct mxs_bch_regs {
 #define        BCH_FLASHLAYOUT0_NBLOCKS_OFFSET                 24
 #define        BCH_FLASHLAYOUT0_META_SIZE_MASK                 (0xff << 16)
 #define        BCH_FLASHLAYOUT0_META_SIZE_OFFSET               16
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
 #define        BCH_FLASHLAYOUT0_ECC0_MASK                      (0x1f << 11)
 #define        BCH_FLASHLAYOUT0_ECC0_OFFSET                    11
 #else
@@ -158,7 +158,7 @@ struct mxs_bch_regs {
 
 #define        BCH_FLASHLAYOUT1_PAGE_SIZE_MASK                 (0xffff << 16)
 #define        BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET               16
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
 #define        BCH_FLASHLAYOUT1_ECCN_MASK                      (0x1f << 11)
 #define        BCH_FLASHLAYOUT1_ECCN_OFFSET                    11
 #else

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 4f37ba7d35eb9776f7a8aff341693e40eff432bd..655e79fbafc0d2d3e870de70ca8d76eb15926ab7 100644 (file)
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -44,7 +44,7 @@ config TI_EDMA3
 
 config APBH_DMA
        bool "Support APBH DMA"
-       depends on MX23 || MX28 || MX6 || MX7
+       depends on MX23 || MX28 || MX6 || MX7 || IMX8M
        help
          Enable APBH DMA driver.
 

diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index 15133128bef95eae74b5fd1ff6a4309ea101ac21..8d17f8f01ddb6fd4a606b4192f44ec534bf13dee 100644 (file)
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -215,7 +215,7 @@ static int mxs_dma_reset(int channel)
 #if defined(CONFIG_MX23)
        uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);
        uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
-#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
        uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set);
        uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
 #endif

diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 23201ca720414bec9a7c308c3667e248e2eb696b..c46fec3d325dbe960420f3ad19065694b2fc2942 100644 (file)
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -259,12 +259,12 @@ config NAND_MXC
 
 config NAND_MXS
        bool "MXS NAND support"
-       depends on MX23 || MX28 || MX6 || MX7
+       depends on MX23 || MX28 || MX6 || MX7 || IMX8M
        select SYS_NAND_SELF_INIT
        imply CMD_NAND
        select APBH_DMA
-       select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7
-       select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7
+       select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8M
+       select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8M
        help
          This enables NAND driver for the NAND flash controller on the
          MXS processors.

diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c
index 2ac06a573068669aee246748ba0f1966a53aae10..facedf92c5c87295229f3f655830dfb2ce6e7e9b 100644 (file)
--- a/drivers/mtd/nand/raw/mxs_nand.c
+++ b/drivers/mtd/nand/raw/mxs_nand.c
@@ -31,7 +31,7 @@
 
 #define        MXS_NAND_DMA_DESCRIPTOR_COUNT           4
 
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
 #define        MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT    2
 #else
 #define        MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT    0
@@ -773,7 +773,7 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
 
                if (status[i] == 0xff) {
                        if (is_mx6dqp() || is_mx7() ||
-                           is_mx6ul())
+                           is_mx6ul() || is_imx8m())
                                if (readl(&bch_regs->hw_bch_debug1))
                                        flag = 1;
                        continue;
@@ -1172,7 +1172,7 @@ int mxs_nand_setup_ecc(struct mtd_info *mtd)
 
        /* Set erase threshold to ecc strength for mx6ul, mx6qp and mx7 */
        if (is_mx6dqp() || is_mx7() ||
-           is_mx6ul())
+           is_mx6ul() || is_imx8m())
                writel(BCH_MODE_ERASE_THRESHOLD(geo->ecc_strength),
                       &bch_regs->hw_bch_mode);
 
@@ -1311,7 +1311,7 @@ int mxs_nand_init_spl(struct nand_chip *nand)
        nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
        nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
 
-       if (is_mx6sx() || is_mx7())
+       if (is_mx6sx() || is_mx7() || is_imx8m())
                nand_info->max_ecc_strength_supported = 62;
        else
                nand_info->max_ecc_strength_supported = 40;