config SYS_CLK_FREQ
- depends on ARC || ARCH_SUNXI
+ depends on ARC || ARCH_SUNXI || MPC83xx
int "CPU clock frequency"
help
TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
if (im->reset.rcwh & HRCWH_PCI_HOST) {
-#if defined(CONFIG_83XX_CLKIN)
- pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
+#if defined(CONFIG_SYS_CLK_FREQ)
+ pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
#else
pci_sync_in = 0xDEADBEEF;
#endif
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
- return CONFIG_83XX_CLKIN * spmf;
+ return CONFIG_SYS_CLK_FREQ * spmf;
}
F: include/configs/MPC8349EMDS.h
F: configs/MPC8349EMDS_defconfig
F: configs/MPC8349EMDS_SDRAM_defconfig
+F: configs/MPC8349EMDS_SLAVE_defconfig
F: board/freescale/mpc837xerdb/
F: include/configs/MPC837XERDB.h
F: configs/MPC837XERDB_defconfig
+F: configs/MPC837XERDB_SLAVE_defconfig
reg32 = 0xff000000;
#endif
if (clk->spmr & SPMR_CKID) {
- /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR
+ /* PCI Clock is half CONFIG_SYS_CLK_FREQ so need to set up OCCR
* fields accordingly */
reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8308RDB=y
CONFIG_FIT=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8313ERDB_NOR=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666667
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8313ERDB_NOR=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8313ERDB_NAND=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
+CONFIG_SYS_CLK_FREQ=66666667
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8313ERDB_NAND=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666667
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8315ERDB=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666667
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8323ERDB=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349EMDS_SDRAM=y
CONFIG_PCI_ONE_PCI1=y
--- /dev/null
+CONFIG_PPC=y
+CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666666
+CONFIG_MPC83xx=y
+CONFIG_TARGET_MPC8349EMDS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
+CONFIG_BOOTDELAY=6
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DATE=y
+# CONFIG_MMC is not set
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHYLIB=y
+# CONFIG_PCI is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349EMDS=y
CONFIG_PCI_ONE_PCI1=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666666
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349ITX=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000"
CONFIG_BOOTDELAY=6
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitxgp:eth0:off console=ttyS0,115200"
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666666
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349ITX=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFEF00000
+CONFIG_SYS_CLK_FREQ=66666666
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349ITX=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC837XEMDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC837XEMDS=y
CONFIG_OF_BOARD_SETUP=y
--- /dev/null
+CONFIG_PPC=y
+CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666667
+CONFIG_MPC83xx=y
+CONFIG_TARGET_MPC837XERDB=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE"
+CONFIG_BOOTDELAY=6
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DATE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_FSL_SATA=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_TSEC_ENET=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666667
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC837XERDB=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="PCIE"
CONFIG_BOOTDELAY=6
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x80000000
+CONFIG_SYS_CLK_FREQ=66666000
CONFIG_MPC83xx=y
CONFIG_TARGET_TQM834X=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF00000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_CADDY2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_IDENT_STRING=" hrcon 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_HRCON=y
CONFIG_CMD_IOLOOP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_IDENT_STRING=" hrcon dh 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_HRCON=y
CONFIG_CMD_IOLOOP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF00000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_IDS8313=y
CONFIG_FIT=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_KMCOGE5NE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_KMETER1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_KMOPTI2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_KMSUPX5=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_KMTEGR1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_KMTEPR2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_KMVECT1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFC000000
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8308_P1M=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_SYS_CLK_FREQ=33000000
CONFIG_MPC83xx=y
CONFIG_TARGET_SBC8349=y
CONFIG_PCI_64BIT=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_SBC8349=y
CONFIG_PCI_64BIT=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_SBC8349=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_IDENT_STRING=" strider con 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
CONFIG_CMD_IOLOOP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_IDENT_STRING=" strider con dp 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
CONFIG_CMD_IOLOOP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_IDENT_STRING=" strider cpu 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
CONFIG_CMD_IOLOOP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_IDENT_STRING=" strider cpu dp 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
CONFIG_CMD_IOLOOP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_SUVD3=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_TUGE1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=32000000
CONFIG_MPC83xx=y
CONFIG_TARGET_VE8313=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF00000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_TARGET_VME8349=y
CONFIG_PCI_64BIT=y
#define CONFIG_TSEC1
#define CONFIG_VSC7385_ENET
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
/*
* Hardware Reset Configuration Word
* if CLKIN is 66.66MHz, then
#define CONFIG_VSC7385_ENET
#define CONFIG_TSEC2
-#ifdef CONFIG_SYS_66MHZ
-#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
-#elif defined(CONFIG_SYS_33MHZ)
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#else
-#error Unknown oscillator frequency.
-#endif
-
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
#define CONFIG_SYS_IMMR 0xE0000000
#if !defined(CONFIG_SPL_BUILD)
HRCWL_DDR_TO_SCB_CLK_2X1 |\
HRCWL_CSB_TO_CLKIN_2X1 |\
HRCWL_CORE_TO_CSB_2X1)
-
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
-
#elif defined(CONFIG_SYS_33MHZ)
/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
HRCWL_DDR_TO_SCB_CLK_2X1 |\
HRCWL_CSB_TO_CLKIN_5X1 |\
HRCWL_CORE_TO_CSB_2X1)
-
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
-
#endif
#define CONFIG_SYS_HRCW_HIGH_BASE (\
HRCWH_FROM_0XFFF00100 |\
HRCWH_ROM_LOC_NAND_SP_8BIT |\
HRCWH_RL_EXT_NAND)
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
/* System IO Config */
#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
#define CONFIG_VSC7385_ENET
#define CONFIG_TSEC2
-#ifdef CONFIG_SYS_66MHZ
-#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
-#elif defined(CONFIG_SYS_33MHZ)
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#else
-#error Unknown oscillator frequency.
-#endif
-
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
#define CONFIG_SYS_IMMR 0xE0000000
#define CONFIG_SYS_MEMTEST_START 0x00001000
HRCWL_CSB_TO_CLKIN_2X1 |\
HRCWL_CORE_TO_CSB_2X1)
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
-
#elif defined(CONFIG_SYS_33MHZ)
/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
HRCWL_CSB_TO_CLKIN_5X1 |\
HRCWL_CORE_TO_CSB_2X1)
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
-
#endif
#define CONFIG_SYS_HRCW_HIGH_BASE (\
HRCWH_FROM_0X00000100 |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_RL_EXT_LEGACY)
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
/* System IO Config */
#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
*/
#define CONFIG_E300 1 /* E300 family */
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
/*
* Hardware Reset Configuration Word
* if CLKIN is 66.66MHz, then
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-#endif
-
/*
* Hardware Reset Configuration Word
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
-/*
- * System Clock Setup
- */
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
-#else
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 66000000
-#endif
-
/*
* Hardware Reset Configuration Word
*/
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_PCI_66M
-#ifdef CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#else
-#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
-#endif
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 66666666 /* in Hz */
-#endif /* CONFIG_PCISLAVE */
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef CONFIG_PCI_66M
-#define CONFIG_SYS_CLK_FREQ 66000000
+#if CONFIG_SYS_CLK_FREQ == 66000000 || CONFIG_SYS_CLK_FREQ == 66666666
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
-#else
-#define CONFIG_SYS_CLK_FREQ 33000000
+#elif CONFIG_SYS_CLK_FREQ == 33000000
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
#endif
-#endif
#define CONFIG_SYS_IMMR 0xE0000000
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_PCI_66M
-#ifdef CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#else
-#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
-#endif
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 66666666 /* in Hz */
-#endif /* CONFIG_PCISLAVE */
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef CONFIG_PCI_66M
-#define CONFIG_SYS_CLK_FREQ 66000000
+#if CONFIG_SYS_CLK_FREQ == 66000000 || CONFIG_SYS_CLK_FREQ == 66666666
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
-#else
-#define CONFIG_SYS_CLK_FREQ 33000000
+#elif CONFIG_SYS_CLK_FREQ == 33000000
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
#endif
-#endif
#define CONFIG_SYS_IMMR 0xE0000000
#endif
-#define CONFIG_PCI_66M
-#ifdef CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN 66666666 /* in Hz */
-#else
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#endif
-
/* TSEC */
#ifdef CONFIG_TSEC_ENET
*/
#define CONFIG_E300 1 /* E300 family */
-/*
- * System Clock Setup
- */
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
-#else
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 66000000
-#endif
-
/*
* Hardware Reset Configuration Word
* if CLKIN is 66MHz, then
*/
#define CONFIG_VSC7385_ENET
-/*
- * System Clock Setup
- */
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 66666667 /* in HZ */
-#else
-#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
-#define CONFIG_PCIE
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-#endif
-
/*
* Hardware Reset Configuration Word
*/
/* IMMR Base Address Register, use Freescale default: 0xff400000 */
#define CONFIG_SYS_IMMR 0xff400000
-/* System clock. Primary input clock when in PCI host mode */
-#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
-
/*
* Local Bus LCRR
* LCRR: DLL bypass, Clock divider is 8
/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-#define CONFIG_PCI_66M
#ifdef CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#else
-#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef CONFIG_PCI_66M
-#define CONFIG_SYS_CLK_FREQ 66000000
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
#else
-#define CONFIG_SYS_CLK_FREQ 33000000
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
#endif
-#endif
#define CONFIG_SYS_IMMR 0xE0000000
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
/*
* Hardware Reset Configuration Word
* if CLKIN is 66.66MHz, then
#define CONFIG_BOOT_RETRY_MIN 30
#define CONFIG_RESET_TO_RETRY
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
#define CONFIG_SYS_IMMR 0xF0000000
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
#include "km/keymile-common.h"
#include "km/km-powerpc.h"
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 66000000
-#define CONFIG_SYS_CLK_FREQ 66000000
-#define CONFIG_83XX_PCICLK 66000000
-
/*
* IMMR new address
*/
#define CONFIG_TSEC1
#define CONFIG_TSEC2
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
/*
* Hardware Reset Configuration Word
* if CLKIN is 66.66MHz, then
/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-/*
- * The default if PCI isn't enabled, or if no PCI clk setting is given
- * is 66MHz; this is what the board defaults to when the PCI slot is
- * physically empty. The board will automatically (i.e w/o jumpers)
- * clock down to 33MHz if you insert a 33MHz PCI card.
- */
#ifdef CONFIG_PCI_33M
-#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
-#else /* 66M */
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef CONFIG_PCI_33M
-#define CONFIG_SYS_CLK_FREQ 33000000
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
#else /* 66M */
-#define CONFIG_SYS_CLK_FREQ 66000000
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
#endif
-#endif
#define CONFIG_SYS_IMMR 0xE0000000
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
/*
* Hardware Reset Configuration Word
* if CLKIN is 66.66MHz, then
* On-board devices
*
*/
-#define CONFIG_83XX_CLKIN 32000000 /* in Hz */
-
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
#define CONFIG_SYS_IMMR 0xE0000000
#define CONFIG_SYS_MEMTEST_START 0x00001000
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
#define CONFIG_PCI_66M
-#ifdef CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#else
-#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
-#endif
-#ifndef CONFIG_SYS_CLK_FREQ
#ifdef CONFIG_PCI_66M
-#define CONFIG_SYS_CLK_FREQ 66000000
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
#else
-#define CONFIG_SYS_CLK_FREQ 33000000
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
#endif
-#endif
#define CONFIG_SYS_IMMR 0xE0000000