ARM: atmel: at91sam9n12ek: enable spl support
authorBo Shen <voice.shen@atmel.com>
Fri, 27 Mar 2015 06:23:36 +0000 (14:23 +0800)
committerAndreas Bießmann <andreas.devel@googlemail.com>
Tue, 31 Mar 2015 23:04:31 +0000 (01:04 +0200)
Enable SPL support for at91sam9n12ek boards, now it supports
boot up from NAND flash, serial flash.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
arch/arm/mach-at91/Kconfig
arch/arm/mach-at91/Makefile
arch/arm/mach-at91/include/mach/at91_pmc.h
arch/arm/mach-at91/mpddrc.c
arch/arm/mach-at91/spl_at91.c
board/atmel/at91sam9n12ek/at91sam9n12ek.c
configs/at91sam9n12ek_nandflash_defconfig
configs/at91sam9n12ek_spiflash_defconfig
include/configs/at91sam9n12ek.h

index bdf87f960588f1aee89d7a522931f7daeea987b8..30c4e17ec94338e9e1afd172140d1cfb9392385d 100644 (file)
@@ -75,6 +75,7 @@ config TARGET_PM9G45
 config TARGET_AT91SAM9N12EK
        bool "Atmel AT91SAM9N12-EK board"
        select CPU_ARM926EJS
+       select SUPPORT_SPL
 
 config TARGET_AT91SAM9RLEK
        bool "Atmel at91sam9rl reference board"
index ba83616d578b005630ff84bce0759b1fe4560a2d..0d3ee48493d99b4073d43402b222406cd722c677 100644 (file)
@@ -2,6 +2,7 @@ obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
 ifneq ($(CONFIG_SPL_BUILD),)
 obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
 obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
+obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
 obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
 obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
 obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
index c903260bf9a5cf7ee32b9ab46cdf0f6a2a655e5d..ebb7decd22e6001ee92e62ff638b3e6210861e86 100644 (file)
@@ -98,7 +98,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_CSS_MASK         0x00000003
 
 #if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
-       defined(CONFIG_AT91SAM9X5)
+       defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
 #define AT91_PMC_MCKR_PRES_1           0x00000000
 #define AT91_PMC_MCKR_PRES_2           0x00000010
 #define AT91_PMC_MCKR_PRES_4           0x00000020
@@ -128,7 +128,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_MDIV_1           0x00000000
 #define AT91_PMC_MCKR_MDIV_2           0x00000100
 #if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
-       defined(CONFIG_AT91SAM9X5)
+       defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
 #define AT91_PMC_MCKR_MDIV_3           0x00000300
 #endif
 #define AT91_PMC_MCKR_MDIV_4           0x00000200
index 24d5fcde02b5ed6a51ba21dd3280e1901cefdad0..e2b6a49eb92f1d7996f9c691ca7af22ed403a139 100644 (file)
@@ -20,7 +20,7 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address)
 static int ddr2_decodtype_is_seq(u32 cr)
 {
 #if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
-       defined(CONFIG_AT91SAM9X5)
+       defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
        if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
                return 0;
 #endif
index e28e568d9d77adcf8ae3a89cd93c71311a330205..a79a9dce75ac6548eb9729ce7d61ac0b49fab8b5 100644 (file)
@@ -115,7 +115,7 @@ void board_init_f(ulong dummy)
        timer_init();
 
        /* enable clocks for all PIOs */
-#ifdef CONFIG_AT91SAM9X5
+#if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
        at91_periph_clk_enable(ATMEL_ID_PIOAB);
        at91_periph_clk_enable(ATMEL_ID_PIOCD);
 #else
index 9adc9920b473bedda137691236cf8c11ccd07522..4f46a0353338be729a01b6d2d71994449bf0214c 100644 (file)
@@ -257,3 +257,76 @@ int dram_init(void)
                                        CONFIG_SYS_SDRAM_SIZE);
        return 0;
 }
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+       at91_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+       at91sam9n12ek_nand_hw_init();
+#elif CONFIG_SYS_USE_SPIFLASH
+       at91_spi0_hw_init(1 << 4);
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+       ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+       ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+                   ATMEL_MPDDRC_CR_NR_ROW_13 |
+                   ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+                   ATMEL_MPDDRC_CR_NB_8BANKS |
+                   ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
+
+       ddr2->rtr = 0x411;
+
+       ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+                     8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+       ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+                     200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+                     19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+                     18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+       ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+                     3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+                     7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+       struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+       struct atmel_mpddr ddr2;
+       unsigned long csa;
+
+       ddr2_conf(&ddr2);
+
+       /* enable DDR2 clock */
+       writel(0x4, &pmc->scer);
+
+       /* Chip select 1 is for DDR2/SDRAM */
+       csa = readl(&matrix->ebicsa);
+       csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+       csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
+       csa |= AT91_MATRIX_EBI_DBPD_OFF;
+       csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+       writel(csa, &matrix->ebicsa);
+
+       /* DDRAM2 Controller initialize */
+       ddr2_init(ATMEL_BASE_CS1, &ddr2);
+}
+#endif
index f908246d3ddc354054d52d37d59d5bf3dce8103c..11b42d4a9d84c3de896a876e6e3f55052b8fb138 100644 (file)
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH"
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
index d106b5a28e18364ba754ecb9e4cdfc66eb8ae226..5426bcd2882754a0d1d00d075778be8baeec6838 100644 (file)
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH"
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
index 058e0e43b5da74a645f2ce0baa2380561d77d290..c44da1c19e57a353ce0db12523e1e13bdf606f4f 100644 (file)
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN  (4 * 1024 * 1024)
-#define CONFIG_STACKSIZE       (32 * 1024)     /* regular stack */
+
+/* SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE           0x300000
+#define CONFIG_SPL_MAX_SIZE            0x6000
+#define CONFIG_SPL_STACK               0x308000
+
+#define CONFIG_SPL_BSS_START_ADDR      0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE                0x80000
+#define CONFIG_SYS_SPL_MALLOC_START    0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x80000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MONITOR_LEN         (512 << 10)
+
+#define CONFIG_SYS_MASTER_CLOCK                132096000
+#define CONFIG_SYS_AT91_PLLA           0x20953f03
+#define CONFIG_SYS_MCKR                        0x1301
+#define CONFIG_SYS_MCKR_CSS            0x1302
+
+#define ATMEL_BASE_MPDDRC              ATMEL_BASE_DDRSDRC
+
+#ifdef CONFIG_SYS_USE_MMC
+#define CONFIG_SPL_LDSCRIPT            arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS     0x400
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME                "u-boot.img"
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE      0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT     64
+#define CONFIG_SYS_NAND_OOBSIZE                64
+#define CONFIG_SYS_NAND_BLOCK_SIZE     0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS  0x0
+#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
+
+#elif CONFIG_SYS_USE_SPIFLASH
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     0x8400
+
+#endif
 
 #endif