}
};
-static void hdmi_write(struct dw_hdmi *hdmi, u8 val, int offset)
+static void dw_hdmi_write(struct dw_hdmi *hdmi, u8 val, int offset)
{
switch (hdmi->reg_io_width) {
case 1:
}
}
-static u8 hdmi_read(struct dw_hdmi *hdmi, int offset)
+static u8 dw_hdmi_read(struct dw_hdmi *hdmi, int offset)
{
switch (hdmi->reg_io_width) {
case 1:
return 0;
}
+static u8 (*hdmi_read)(struct dw_hdmi *hdmi, int offset) = dw_hdmi_read;
+static void (*hdmi_write)(struct dw_hdmi *hdmi, u8 val, int offset) =
+ dw_hdmi_write;
+
static void hdmi_mod(struct dw_hdmi *hdmi, unsigned reg, u8 mask, u8 data)
{
u8 val = hdmi_read(hdmi, reg) & ~mask;
HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
+ if (hdmi->write_reg)
+ hdmi_write = hdmi->write_reg;
+
+ if (hdmi->read_reg)
+ hdmi_read = hdmi->read_reg;
+
hdmi_write(hdmi, ih_mute, HDMI_IH_MUTE);
/* enable i2c master done irq */
u8 reg_io_width;
int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
+ void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset);
+ u8 (*read_reg)(struct dw_hdmi *hdmi, int offset);
};
int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock);