ARM: DT: stm32f7: add sdram pin contol node

Also added DT binding doc for stm32 fmc(flexible memory controller).

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts
index 07e0ca70210099e71dc830d1932e5c7993197db9..5846b0d7e74a12b0fba9a13b86073bdea6568dde 100644 (file)
--- a/arch/arm/dts/stm32f746-disco.dts
+++ b/arch/arm/dts/stm32f746-disco.dts
@@ -1,5 +1,6 @@
 /*
  * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
+ * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
  *
  * Based on:
  * stm32f469-disco.dts from Linux
@@ -76,6 +77,12 @@
        status = "okay";
 };
 
+&fmc {
+       pinctrl-0 = <&fmc_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
 &mac {
        status = "okay";
        pinctrl-0 = <&ethernet_mii>;

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 883f818578c144cc7c48bfdd6392e0b07abd3c65..3707550b039dd27ac381f8216f56d9815b5fa3e4 100644 (file)
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -1,5 +1,6 @@
 /*
  * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
+ * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
  *
  * Based on:
  * stm32f429.dtsi from Linux
@@ -70,6 +71,12 @@
                        status = "disabled";
                };
 
+               fmc: fmc@A0000000 {
+                       compatible = "st,stm32-fmc";
+                       reg = <0xA0000000 0x1000>;
+                       u-boot,dm-pre-reloc;
+               };
+
                qspi: quadspi@A0001000 {
                        compatible = "st,stm32-qspi";
                        #address-cells = <1>;
@@ -143,6 +150,55 @@
                                        slew-rate = <2>;
                                };
                        };
+
+                       fmc_pins: fmc@0 {
+                               pins {
+                                       pinmux = <STM32F746_PD10_FUNC_FMC_D15>,
+                                                <STM32F746_PD9_FUNC_FMC_D14>,
+                                                <STM32F746_PD8_FUNC_FMC_D13>,
+                                                <STM32F746_PE15_FUNC_FMC_D12>,
+                                                <STM32F746_PE14_FUNC_FMC_D11>,
+                                                <STM32F746_PE13_FUNC_FMC_D10>,
+                                                <STM32F746_PE12_FUNC_FMC_D9>,
+                                                <STM32F746_PE11_FUNC_FMC_D8>,
+                                                <STM32F746_PE10_FUNC_FMC_D7>,
+                                                <STM32F746_PE9_FUNC_FMC_D6>,
+                                                <STM32F746_PE8_FUNC_FMC_D5>,
+                                                <STM32F746_PE7_FUNC_FMC_D4>,
+                                                <STM32F746_PD1_FUNC_FMC_D3>,
+                                                <STM32F746_PD0_FUNC_FMC_D2>,
+                                                <STM32F746_PD15_FUNC_FMC_D1>,
+                                                <STM32F746_PD14_FUNC_FMC_D0>,
+
+                                                <STM32F746_PE1_FUNC_FMC_NBL1>,
+                                                <STM32F746_PE0_FUNC_FMC_NBL0>,
+
+                                                <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
+                                                <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
+
+                                                <STM32F746_PG1_FUNC_FMC_A11>,
+                                                <STM32F746_PG0_FUNC_FMC_A10>,
+                                                <STM32F746_PF15_FUNC_FMC_A9>,
+                                                <STM32F746_PF14_FUNC_FMC_A8>,
+                                                <STM32F746_PF13_FUNC_FMC_A7>,
+                                                <STM32F746_PF12_FUNC_FMC_A6>,
+                                                <STM32F746_PF5_FUNC_FMC_A5>,
+                                                <STM32F746_PF4_FUNC_FMC_A4>,
+                                                <STM32F746_PF3_FUNC_FMC_A3>,
+                                                <STM32F746_PF2_FUNC_FMC_A2>,
+                                                <STM32F746_PF1_FUNC_FMC_A1>,
+                                                <STM32F746_PF0_FUNC_FMC_A0>,
+
+                                                <STM32F746_PH3_FUNC_FMC_SDNE0>,
+                                                <STM32F746_PH5_FUNC_FMC_SDNWE>,
+                                                <STM32F746_PF11_FUNC_FMC_SDNRAS>,
+                                                <STM32F746_PG15_FUNC_FMC_SDNCAS>,
+                                                <STM32F746_PC3_FUNC_FMC_SDCKE0>,
+                                                <STM32F746_PG8_FUNC_FMC_SDCLK>;
+                                       slew-rate = <2>;
+                               };
+                       };
+
                };
        };
 };

diff --git a/doc/device-tree-bindings/ram/st,stm32-fmc.txt b/doc/device-tree-bindings/ram/st,stm32-fmc.txt
new file mode 100644 (file)
index 0000000..3d1392c
--- /dev/null
+++ b/doc/device-tree-bindings/ram/st,stm32-fmc.txt
@@ -0,0 +1,51 @@
+ST, stm32 flexible memory controller Drive
+Required properties:
+- compatible   : "st,stm32-fmc"
+- reg          : fmc controller base address
+- clocks       : fmc controller clock
+u-boot,dm-pre-reloc: flag to initialize memory before relocation.
+
+on-board sdram memory attributes:
+- st,sdram-control : parameters for sdram configuration, in this order:
+  number of columns
+  number of rows
+  memory width
+  number of intenal banks in memory
+  cas latency
+  read burst enable or disable
+  read pipe delay
+
+- st,sdram-timing: timings for sdram, in this order:
+  tmrd
+  txsr
+  tras
+  trc
+  trp
+  trcd
+
+There is device tree include file at :
+include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing
+parameters as MACROS.
+
+Example:
+       fmc: fmc@A0000000 {
+            compatible = "st,stm32-fmc";
+            reg = <0xA0000000 0x1000>;
+            clocks = <&rcc 0 64>;
+            u-boot,dm-pre-reloc;
+       };
+
+       &fmc {
+               pinctrl-0 = <&fmc_pins>;
+               pinctrl-names = "default";
+               status = "okay";
+
+               mr-nbanks = <1>;
+               /* sdram memory configuration from sdram datasheet */
+       bank1: bank@0 {
+              st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
+                                               CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
+              st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
+                                               TRCD_18>;
+       };
+}