arm: socfpga: Enable SPL_DM_SEQ_ALIAS for all SOCFPGA configs
authorNathan Rossi <nathan@nathanrossi.com>
Thu, 7 Jan 2016 17:00:48 +0000 (03:00 +1000)
committerMichal Simek <michal.simek@xilinx.com>
Wed, 13 Jan 2016 12:20:03 +0000 (13:20 +0100)
This feature is required in SPL to enable support for loading from SPI
flash.

Also clean up the #define in socfpga_common.h.

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin-Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
configs/socfpga_arria5_defconfig
configs/socfpga_cyclone5_defconfig
configs/socfpga_sockit_defconfig
configs/socfpga_socrates_defconfig
configs/socfpga_sr1500_defconfig
include/configs/socfpga_common.h

index 68d12df404ca3c516d63a593b85363a843f84e54..6e8976fcc35966ba646f5a799f65a7e44a9fc23b 100644 (file)
@@ -7,6 +7,7 @@ CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
 CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
 CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_STACK_R=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
index accee924a32a8975c59ed340fb9afe273f345157..e31aa716893a1a60d9cd3b169d495eeb2b2b1898 100644 (file)
@@ -7,6 +7,7 @@ CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
 CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
 CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_STACK_R=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
index b4f41a939d1ab1c77071ec39a65769b86cc9cb69..59fbb2c3c1292e461ab273e7b3e87e7b207ce482 100644 (file)
@@ -7,6 +7,7 @@ CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
 CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
 CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_STACK_R=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
index fe940f967a6cab9433c44baadcd95ac7a6ee19f6..aaba8cb29d5336e365a1e5550d3624f1afc8c55b 100644 (file)
@@ -7,6 +7,7 @@ CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
 CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
 CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_STACK_R=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
index 3d98a636d911796b2f090617a794bc2a817e7662..a4f0835e9da3bad3cfd869f58e8069d4e7b4fa46 100644 (file)
@@ -6,6 +6,7 @@ CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_SR1500=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
 CONFIG_SPL=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_ADDR=0x00800000
 # CONFIG_CMD_IMLS is not set
index a09e906a6be944c7f14fce511b637c8dec3de10f..8de0ab90469d6e35952cefef8fb59cea01affb09 100644 (file)
@@ -370,7 +370,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 
 /* SPL QSPI boot support */
 #ifdef CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_DM_SEQ_ALIAS            1
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x40000