ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configuration

Update to existing recommendation for L2ACTLR configuration to prevent
system instability and optimize performance.

These apply to both OMAP5 and DRA7.

Reported-by: Vivek Chengalvala <vchengalvala@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index f8060555b680b4171badccfe1bc77a00daf3bc91..8d6b59eeb04406bc3bf23c4714d41bde89585dce 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -304,6 +304,21 @@ void config_data_eye_leveling_samples(u32 emif_base)
                       (*ctrl)->control_emif2_sdram_config_ext);
 }
 
+void init_cpu_configuration(void)
+{
+       u32 l2actlr;
+
+       asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
+       /*
+        * L2ACTLR: Ensure to enable the following:
+        * 3: Disable clean/evict push to external
+        * 4: Disable WriteUnique and WriteLineUnique transactions from master
+        * 8: Disable DVM/CMO message broadcast
+        */
+       l2actlr |= 0x118;
+       omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
+}
+
 void init_omap_revision(void)
 {
        /*
@@ -342,6 +357,7 @@ void init_omap_revision(void)
        default:
                *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
        }
+       init_cpu_configuration();
 }
 
 void reset_cpu(ulong ignored)