mxs: spl_mem_init: Change EMI port priority

FSL bootlets code set the PORT_PRIORITY_ORDER field of register HW_EMI_CTRL
as 0x2, which means:

PORT0231 = 0x02 Priority Order: AXI0, AHB2, AHB3, AHB1

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index 5eacd36867d6dfbc1ee1a3c7f4727ec07d67a802..41fb803918d2c1facee3a6d1df002ee2d3e567a8 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -287,7 +287,7 @@ static void mx23_mem_init(void)
        early_delay(20000);
 
        /* Adjust EMI port priority. */
-       clrsetbits_le32(0x80020000, 0x1f << 16, 0x8);
+       clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
        early_delay(20000);
 
        setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);