ARM: kirkwood: remove kw_config_adr_windows

Now that kirkwood is using the mvebu mbus this function is no longer
needed.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c
index 009b49287b7ff96e366417791c3c06732a6294a6..8b21db10715364f33f7d50abcd2cd001822e6045 100644 (file)
--- a/arch/arm/mach-kirkwood/cpu.c
+++ b/arch/arm/mach-kirkwood/cpu.c
@@ -46,70 +46,6 @@ unsigned int kw_winctrl_calcsize(unsigned int sizeval)
        return (0x0000ffff & j);
 }
 
-/*
- * kw_config_adr_windows - Configure address Windows
- *
- * There are 8 address windows supported by Kirkwood Soc to addess different
- * devices. Each window can be configured for size, BAR and remap addr
- * Below configuration is standard for most of the cases
- *
- * If remap function not used, remap_lo must be set as base
- *
- * Reference Documentation:
- * Mbus-L to Mbus Bridge Registers Configuration.
- * (Sec 25.1 and 25.3 of Datasheet)
- */
-int kw_config_adr_windows(void)
-{
-       struct kwwin_registers *winregs =
-               (struct kwwin_registers *)MVEBU_CPU_WIN_BASE;
-
-       /* Window 0: PCIE MEM address space */
-       writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
-               KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
-
-       writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
-       writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
-       writel(0x0, &winregs[0].remap_hi);
-
-       /* Window 1: PCIE IO address space */
-       writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
-               KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
-       writel(KW_DEFADR_PCI_IO, &winregs[1].base);
-       writel(KW_DEFADR_PCI_IO, &winregs[1].remap_lo);
-       writel(0x0, &winregs[1].remap_hi);
-
-       /* Window 2: NAND Flash address space */
-       writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
-               KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
-       writel(KW_DEFADR_NANDF, &winregs[2].base);
-       writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
-       writel(0x0, &winregs[2].remap_hi);
-
-       /* Window 3: SPI Flash address space */
-       writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
-               KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
-       writel(KW_DEFADR_SPIF, &winregs[3].base);
-       writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
-       writel(0x0, &winregs[3].remap_hi);
-
-       /* Window 4: BOOT Memory address space */
-       writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
-               KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
-       writel(KW_DEFADR_BOOTROM, &winregs[4].base);
-
-       /* Window 5: Security SRAM address space */
-       writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
-               KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
-       writel(KW_DEFADR_SASRAM, &winregs[5].base);
-
-       /* Window 6-7: Disabled */
-       writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
-       writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
-
-       return 0;
-}
-
 static struct mbus_win windows[] = {
        /* Window 0: PCIE MEM address space */
        { KW_DEFADR_PCI_MEM, 1024 * 1024 * 256,

diff --git a/arch/arm/mach-kirkwood/include/mach/cpu.h b/arch/arm/mach-kirkwood/include/mach/cpu.h
index 3d6b15568a8a8db0062f4e5d7303410c48e56814..ea42182cf9c609332bc5d88c5c829f28468a9f07 100644 (file)
--- a/arch/arm/mach-kirkwood/include/mach/cpu.h
+++ b/arch/arm/mach-kirkwood/include/mach/cpu.h
@@ -150,7 +150,6 @@ extern struct mvebu_mbus_state mbus_state;
 unsigned int mvebu_sdram_bar(enum memory_bank bank);
 unsigned int mvebu_sdram_bs(enum memory_bank bank);
 void mvebu_sdram_size_adjust(enum memory_bank bank);
-int kw_config_adr_windows(void);
 int mvebu_mbus_probe(struct mbus_win windows[], int count);
 void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
                unsigned int gpp0_oe, unsigned int gpp1_oe);