powerpc/p2041: fix serdes reference clock frequency display for PC board

PC board has different serdes clock setting with PB board, it uses same
serdes frequency setting on bank2 as on bank1. PC board can be distingushed
from PB board by checking CPLD version, if running on PC board, then fix
the serdes reference clock frequency of bank2.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index a706a6d00ca6fd2ce6b5533442a6c8b3d38d5394..44d3e0c618bf62a98b6ed048e40e81f4ea696456 100644 (file)
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -227,6 +227,17 @@ int misc_init_r(void)
                                "'00' is unsupported\n");
                else
                        actual[i] = freq[i][clock];
+
+               /*
+                * PC board uses a different CPLD with PB board, this CPLD
+                * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
+                * board has cpld_ver_sub = 0, and pcba_ver = 4.
+                */
+               if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
+                   (CPLD_READ(pcba_ver) == 5)) {
+                       /* PC board bank2 frequency */
+                       actual[i] = freq[i-1][clock];
+               }
        }
 
        for (i = 0; i < NUM_SRDS_BANKS; i++) {