ARM: keystone2: Add additional fields used for DDR3 configuration

Future boards will need to configure DDR3 registers in a slightly
different manner. Support this by defining additional variables and
defines that will be utilized later.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/mach-keystone/include/mach/ddr3.h b/arch/arm/mach-keystone/include/mach/ddr3.h
index 5feffe825b97e6bda43510d5f526fcbfdf050ad5..93789fd456535b56b92ab00b9c41ee58d9a34a40 100644 (file)
--- a/arch/arm/mach-keystone/include/mach/ddr3.h
+++ b/arch/arm/mach-keystone/include/mach/ddr3.h
@@ -35,6 +35,20 @@ struct ddr3_phy_config {
        unsigned int zq1cr1;
        unsigned int zq2cr1;
        unsigned int pir_v1;
+       unsigned int datx8_2_mask;
+       unsigned int datx8_2_val;
+       unsigned int datx8_3_mask;
+       unsigned int datx8_3_val;
+       unsigned int datx8_4_mask;
+       unsigned int datx8_4_val;
+       unsigned int datx8_5_mask;
+       unsigned int datx8_5_val;
+       unsigned int datx8_6_mask;
+       unsigned int datx8_6_val;
+       unsigned int datx8_7_mask;
+       unsigned int datx8_7_val;
+       unsigned int datx8_8_mask;
+       unsigned int datx8_8_val;
        unsigned int pir_v2;
 };
 

diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index 38d019056a29df27fdbb2d01c43c84e244c7381c..1969a10ab377d464dd2348cad59e73341ca54d26 100644 (file)
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -52,6 +52,8 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_DDRPHY_ZQ2CR1_OFFSET        0x1A4
 #define KS2_DDRPHY_ZQ3CR1_OFFSET        0x1B4
 
+#define KS2_DDRPHY_DATX8_2_OFFSET       0x240
+#define KS2_DDRPHY_DATX8_3_OFFSET       0x280
 #define KS2_DDRPHY_DATX8_4_OFFSET       0x2C0
 #define KS2_DDRPHY_DATX8_5_OFFSET       0x300
 #define KS2_DDRPHY_DATX8_6_OFFSET       0x340
@@ -70,6 +72,7 @@ typedef volatile unsigned int   *dv_reg_p;
 #define PDQ_MASK                        0x00000070
 #define NOSRA_MASK                      0x08000000
 #define ECC_MASK                        0x00000001
+#define DXEN_MASK                       0x00000001
 
 /* DDR3 definitions */
 #define KS2_DDR3A_EMIF_CTRL_BASE       0x21010000