*/
struct generic_ecam_pcie {
void *cfg_base;
+ pci_size_t size;
+ int first_busno;
};
/**
void *addr;
addr = pcie->cfg_base;
- addr += PCI_BUS(bdf) << 20;
+ addr += (PCI_BUS(bdf) - pcie->first_busno) << 20;
addr += PCI_DEV(bdf) << 15;
addr += PCI_FUNC(bdf) << 12;
addr += offset;
return 0;
}
+static bool pci_generic_ecam_addr_valid(const struct udevice *bus,
+ pci_dev_t bdf)
+{
+ struct generic_ecam_pcie *pcie = dev_get_priv(bus);
+ int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16);
+
+ return (PCI_BUS(bdf) >= pcie->first_busno &&
+ PCI_BUS(bdf) < pcie->first_busno + num_buses);
+}
+
/**
* pci_generic_ecam_read_config() - Read from configuration space
* @bus: Pointer to the PCI bus
pci_dev_t bdf, uint offset,
ulong *valuep, enum pci_size_t size)
{
+ if (!pci_generic_ecam_addr_valid(bus, bdf)) {
+ *valuep = pci_get_ff(size);
+ return 0;
+ }
+
return pci_generic_mmap_read_config(bus, pci_generic_ecam_conf_address,
bdf, offset, valuep, size);
}
uint offset, ulong value,
enum pci_size_t size)
{
+ if (!pci_generic_ecam_addr_valid(bus, bdf))
+ return 0;
+
return pci_generic_mmap_write_config(bus, pci_generic_ecam_conf_address,
bdf, offset, value, size);
}
return err;
}
- pcie->cfg_base = map_physmem(reg_res.start,
- fdt_resource_size(®_res),
- MAP_NOCACHE);
+ pcie->size = fdt_resource_size(®_res);
+ pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE);
+
+ return 0;
+}
+
+static int pci_generic_ecam_probe(struct udevice *dev)
+{
+ struct generic_ecam_pcie *pcie = dev_get_priv(dev);
+
+ pcie->first_busno = dev->seq;
return 0;
}
.id = UCLASS_PCI,
.of_match = pci_generic_ecam_ids,
.ops = &pci_generic_ecam_ops,
+ .probe = pci_generic_ecam_probe,
.ofdata_to_platdata = pci_generic_ecam_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct generic_ecam_pcie),
};