arm64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe

- Enabling GTR lane-0 to PCIe
- Enabling PCIe node in device tree

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index fd7d6466711bfea8b6aeba1bdd76ea1f54316d18..df916d0f77d5c4125b9e43daf901c39887211c35 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -168,7 +168,7 @@
                gtr_sel0 {
                        gpio-hog;
                        gpios = <0 0>;
-                       output-high; /* PCIE = 0, DP = 1 */
+                       output-low; /* PCIE = 0, DP = 1 */
                        line-name = "sel0";
                };
                gtr_sel1 {
@@ -551,7 +551,7 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 };
 
 &pcie {
-/*     status = "okay"; */
+       status = "okay";
 };
 
 &qspi {