AT91: Board fix for AT91SAM9261-EK
authorXu, Hong <Hong.Xu@atmel.com>
Sun, 31 Jul 2011 22:49:00 +0000 (22:49 +0000)
committerU-Boot <uboot@aari01-12.(none)>
Wed, 3 Aug 2011 11:00:56 +0000 (13:00 +0200)
Fix board part of AT91SAM9261-EK according to the new scheme

Signed-off-by: Hong Xu <hong.xu@atmel.com>
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
Makefile
board/atmel/at91sam9261ek/at91sam9261ek.c
board/atmel/at91sam9261ek/config.mk [deleted file]
board/atmel/at91sam9261ek/led.c
boards.cfg
include/configs/at91sam9261ek.h

index 54b880432839aae97a727c42540b0c38a3058688..28398a39d49c0d61fbedd4c0020706fe65e93b84 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -802,29 +802,6 @@ M5485HFE_config :  unconfig
 ## ARM926EJ-S Systems
 #########################################################################
 
-at91sam9261ek_nandflash_config \
-at91sam9261ek_dataflash_cs0_config \
-at91sam9261ek_dataflash_cs3_config \
-at91sam9261ek_config \
-at91sam9g10ek_nandflash_config \
-at91sam9g10ek_dataflash_cs0_config \
-at91sam9g10ek_dataflash_cs3_config \
-at91sam9g10ek_config   :       unconfig
-       @mkdir -p $(obj)include
-       @if [ "$(findstring 9g10,$@)" ] ; then \
-               echo "#define CONFIG_AT91SAM9G10EK 1"   >>$(obj)include/config.h ; \
-       else \
-               echo "#define CONFIG_AT91SAM9261EK 1"   >>$(obj)include/config.h ; \
-       fi;
-       @if [ "$(findstring _nandflash,$@)" ] ; then \
-               echo "#define CONFIG_SYS_USE_NANDFLASH 1"       >>$(obj)include/config.h ; \
-       elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
-               echo "#define CONFIG_SYS_USE_DATAFLASH_CS3 1"   >>$(obj)include/config.h ; \
-       else \
-               echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1"   >>$(obj)include/config.h ; \
-       fi;
-       @$(MKCONFIG) -n $@ -a at91sam9261ek arm arm926ejs at91sam9261ek atmel at91
-
 at91sam9263ek_norflash_config \
 at91sam9263ek_norflash_boot_config \
 at91sam9263ek_nandflash_config \
index de5cfaeb00ae941dd369dd03b00f787d4761f8d7..b6c7d9e02c5c576aca2d1aa816c43e1c1ca11cf7 100644 (file)
@@ -23,6 +23,7 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/arch/at91sam9261.h>
 #include <asm/arch/at91sam9261_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
@@ -31,7 +32,6 @@
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
 #include <lcd.h>
 #include <atmel_lcdc.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
@@ -49,44 +49,48 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_CMD_NAND
 static void at91sam9261ek_nand_hw_init(void)
 {
+       struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+       struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
        unsigned long csa;
 
        /* Enable CS3 */
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
-       at91_sys_write(AT91_MATRIX_EBICSA,
-                      csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+       csa = readl(&matrix->ebicsa);
+       csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+
+       writel(csa, &matrix->ebicsa);
 
        /* Configure SMC CS3 for NAND/SmartMedia */
 #ifdef CONFIG_AT91SAM9G10EK
-       at91_sys_write(AT91_SMC_SETUP(3),
-                      AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
-                      AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
-       at91_sys_write(AT91_SMC_PULSE(3),
-                      AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(7) |
-                      AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(7));
-       at91_sys_write(AT91_SMC_CYCLE(3),
-                      AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+       writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+               AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+               &smc->cs[3].setup);
+       writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
+               AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
+               &smc->cs[3].pulse);
+       writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+               &smc->cs[3].cycle);
 #else
-       at91_sys_write(AT91_SMC_SETUP(3),
-                      AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
-                      AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
-       at91_sys_write(AT91_SMC_PULSE(3),
-                      AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
-                      AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
-       at91_sys_write(AT91_SMC_CYCLE(3),
-                      AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+       writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+               AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+               &smc->cs[3].setup);
+       writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+               AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+               &smc->cs[3].pulse);
+       writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+               &smc->cs[3].cycle);
 #endif
-       at91_sys_write(AT91_SMC_MODE(3),
-                      AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-                      AT91_SMC_EXNWMODE_DISABLE |
+       writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+                      AT91_SMC_MODE_EXNW_DISABLE |
 #ifdef CONFIG_SYS_NAND_DBW_16
-                      AT91_SMC_DBW_16 |
+                      AT91_SMC_MODE_DBW_16 |
 #else /* CONFIG_SYS_NAND_DBW_8 */
-                      AT91_SMC_DBW_8 |
+                      AT91_SMC_MODE_DBW_8 |
 #endif
-                      AT91_SMC_TDF_(2));
+                      AT91_SMC_MODE_TDF_CYCLE(2),
+                      &smc->cs[3].mode);
 
-       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
+       writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
 
        /* Configure RDY/BSY */
        at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -102,35 +106,37 @@ static void at91sam9261ek_nand_hw_init(void)
 #ifdef CONFIG_DRIVER_DM9000
 static void at91sam9261ek_dm9000_hw_init(void)
 {
+       struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
        /* Configure SMC CS2 for DM9000 */
 #ifdef CONFIG_AT91SAM9G10EK
-       at91_sys_write(AT91_SMC_SETUP(2),
-                      AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(0) |
-                      AT91_SMC_NRDSETUP_(3) | AT91_SMC_NCS_RDSETUP_(0));
-       at91_sys_write(AT91_SMC_PULSE(2),
-                      AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(8) |
-                      AT91_SMC_NRDPULSE_(6) | AT91_SMC_NCS_RDPULSE_(8));
-       at91_sys_write(AT91_SMC_CYCLE(2),
-                      AT91_SMC_NWECYCLE_(20) | AT91_SMC_NRDCYCLE_(20));
-       at91_sys_write(AT91_SMC_MODE(2),
-                      AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-                      AT91_SMC_EXNWMODE_DISABLE |
-                      AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
-                      AT91_SMC_TDF_(1));
+       writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
+               AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0),
+               &smc->cs[2].setup);
+       writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) |
+               AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8),
+               &smc->cs[2].pulse);
+       writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
+               &smc->cs[2].cycle);
+       writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+                      AT91_SMC_MODE_EXNW_DISABLE |
+                      AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+                      AT91_SMC_MODE_TDF_CYCLE(1),
+                      &smc->cs[2].mode);
 #else
-       at91_sys_write(AT91_SMC_SETUP(2),
-                      AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
-                      AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
-       at91_sys_write(AT91_SMC_PULSE(2),
-                      AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
-                      AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
-       at91_sys_write(AT91_SMC_CYCLE(2),
-                      AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
-       at91_sys_write(AT91_SMC_MODE(2),
-                      AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-                      AT91_SMC_EXNWMODE_DISABLE |
-                      AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
-                      AT91_SMC_TDF_(1));
+       writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
+               AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+               &smc->cs[2].setup);
+       writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
+               AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
+               &smc->cs[2].pulse);
+       writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
+               &smc->cs[2].cycle);
+       writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+                      AT91_SMC_MODE_EXNW_DISABLE |
+                      AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+                      AT91_SMC_MODE_TDF_CYCLE(1),
+                      &smc->cs[2].mode);
 #endif
 
        /* Configure Reset signal as output */
@@ -156,7 +162,7 @@ vidinfo_t panel_info = {
        vl_vsync_len:   1,
        vl_upper_margin:1,
        vl_lower_margin:0,
-       mmio:           AT91SAM9261_LCDC_BASE,
+       mmio:           ATMEL_BASE_LCDC,
 };
 
 void lcd_enable(void)
@@ -171,6 +177,8 @@ void lcd_disable(void)
 
 static void at91sam9261ek_lcd_hw_init(void)
 {
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
        at91_set_A_periph(AT91_PIN_PB1, 0);     /* LCDHSYNC */
        at91_set_A_periph(AT91_PIN_PB2, 0);     /* LCDDOTCK */
        at91_set_A_periph(AT91_PIN_PB3, 0);     /* LCDDEN */
@@ -194,12 +202,11 @@ static void at91sam9261ek_lcd_hw_init(void)
        at91_set_B_periph(AT91_PIN_PB27, 0);    /* LCDD22 */
        at91_set_B_periph(AT91_PIN_PB28, 0);    /* LCDD23 */
 
-       at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
+       writel(AT91_PMC_HCK1, &pmc->scer);
 
-#ifdef CONFIG_AT91SAM9G10EK
-       gd->fb_base = CONFIG_AT91SAM9G10_LCD_BASE;
-#else
-       gd->fb_base = AT91SAM9261_SRAM_BASE;
+       /* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
+#ifdef CONFIG_AT91SAM9261EK
+       gd->fb_base = ATMEL_BASE_SRAM;
 #endif
 }
 
@@ -217,7 +224,7 @@ void lcd_show_board_info(void)
        lcd_printf ("(C) 2008 ATMEL Corp\n");
        lcd_printf ("at91support@atmel.com\n");
        lcd_printf ("%s CPU at %s MHz\n",
-               CONFIG_SYS_AT91_CPU_NAME,
+               ATMEL_CPU_NAME,
                strmhz(temp, get_cpu_clk_rate()));
 
        dram_size = 0;
@@ -246,9 +253,9 @@ int board_init(void)
        gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
 #endif
        /* adress of boot parameters */
-       gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+       gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-       at91_serial_hw_init();
+       at91_seriald_hw_init();
 #ifdef CONFIG_CMD_NAND
        at91sam9261ek_nand_hw_init();
 #endif
@@ -273,8 +280,9 @@ int board_eth_init(bd_t *bis)
 
 int dram_init(void)
 {
-       gd->bd->bi_dram[0].start = PHYS_SDRAM;
-       gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+       gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+               CONFIG_SYS_SDRAM_SIZE);
+
        return 0;
 }
 
diff --git a/board/atmel/at91sam9261ek/config.mk b/board/atmel/at91sam9261ek/config.mk
deleted file mode 100644 (file)
index e554a45..0000000
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x23f00000
index 5d1c5f2f8baf85a67d83be42230f30602ec39a6f..0c2f522825c5d0a6c7d404a4835127da07eadb9c 100644 (file)
 #include <asm/arch/at91sam9261.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/io.h>
 
 void coloured_LED_init(void)
 {
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
        /* Enable clock */
-       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA);
+       writel(ATMEL_ID_PIOA, &pmc->pcer);
 
        at91_set_gpio_output(CONFIG_RED_LED, 1);
        at91_set_gpio_output(CONFIG_GREEN_LED, 1);
index 8a5a618416c7b7f703e301d270adea7d33e8438e..f77ecfcd304c2d465030357f514f869674a7c7fc 100644 (file)
@@ -77,6 +77,12 @@ at91cap9adk                  arm         arm926ejs   -                   atmel
 at91sam9260ek_nandflash      arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH
 at91sam9260ek_dataflash_cs0  arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0
 at91sam9260ek_dataflash_cs1  arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1
+at91sam9261ek_nandflash      arm         arm926ejs   at91sam9261ek       atmel          at91        at91sam9261ek:AT91SAM9261,SYS_USE_NANDFLASH
+at91sam9261ek_dataflash_cs0  arm         arm926ejs   at91sam9261ek       atmel          at91        at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS0
+at91sam9261ek_dataflash_cs3  arm         arm926ejs   at91sam9261ek       atmel          at91        at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS3
+at91sam9g10ek_nandflash      arm         arm926ejs   at91sam9261ek       atmel          at91        at91sam9261ek:AT91SAM9G10,SYS_USE_NANDFLASH
+at91sam9g10ek_dataflash_cs0  arm         arm926ejs   at91sam9261ek       atmel          at91        at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS0
+at91sam9g10ek_dataflash_cs3  arm         arm926ejs   at91sam9261ek       atmel          at91        at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS3
 at91sam9g20ek_nandflash      arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH
 at91sam9g20ek_dataflash_cs0  arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0
 at91sam9g20ek_dataflash_cs1  arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1
index 401478b270571d2e127af55a37b4a99dfbeab9e1..126907f445c093c7a096e3a94f031ea8741daf0f 100644 (file)
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_AT91_LEGACY
-
 /* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK     32768           /* slow clock xtal */
 #define CONFIG_SYS_AT91_MAIN_CLOCK     18432000        /* 18.432 MHz crystal */
-#define CONFIG_SYS_HZ          1000
+#define CONFIG_SYS_HZ                  1000
 
-#define CONFIG_ARM926EJS       1       /* This is an ARM926EJS Core    */
-#ifdef CONFIG_AT91SAM9G10EK
-#define CONFIG_AT91SAM9G10     1       /* It's an Atmel AT91SAM9G10 SoC*/
+#ifdef CONFIG_AT91SAM9G10
+#define CONFIG_AT91SAM9G10EK           /* It's an Atmel AT91SAM9G10 EK*/
 #else
-#define CONFIG_AT91SAM9261     1       /* It's an Atmel AT91SAM9261 SoC*/
+#define CONFIG_AT91SAM9261EK           /* It's an Atmel AT91SAM9261 EK*/
 #endif
+
+#include <asm/hardware.h>
+
 #define CONFIG_ARCH_CPU_INIT
 #undef CONFIG_USE_IRQ                  /* we don't need IRQ/FIQ stuff  */
 
-#define CONFIG_CMDLINE_TAG     1       /* enable passing of ATAGs      */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG      1
+#define CONFIG_CMDLINE_TAG             /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_ATMEL_LEGACY
+#define CONFIG_SYS_TEXT_BASE           0x21f00000
+
 /*
  * Hardware drivers
  */
-#define CONFIG_AT91_GPIO       1
-#define CONFIG_ATMEL_USART     1
-#undef CONFIG_USART0
-#undef CONFIG_USART1
-#undef CONFIG_USART2
-#define CONFIG_USART3          1       /* USART 3 is DBGU */
+
+/* gpio */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP                1
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE              ATMEL_BASE_DBGU
+#define CONFIG_USART_ID                        ATMEL_ID_SYS
+#define CONFIG_BAUDRATE                        115200
+#define CONFIG_SYS_BAUDRATE_TABLE      {115200, 57600, 38400, 19200, 9600}
 
 /* LCD */
-#define CONFIG_LCD                     1
+#define CONFIG_LCD
 #define LCD_BPP                                LCD_COLOR8
-#define CONFIG_LCD_LOGO                        1
+#define CONFIG_LCD_LOGO
 #undef LCD_TEST_PATTERN
-#define CONFIG_LCD_INFO                        1
-#define CONFIG_LCD_INFO_BELOW_LOGO     1
-#define CONFIG_SYS_WHITE_ON_BLACK              1
-#define CONFIG_ATMEL_LCD               1
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_ATMEL_LCD
 #ifdef CONFIG_AT91SAM9261EK
-#define CONFIG_ATMEL_LCD_BGR555                1
-#else
-#define        CONFIG_AT91SAM9G10_LCD_BASE             0x23E00000      /* LCD is no more in SRAM */
+#define CONFIG_ATMEL_LCD_BGR555
 #endif
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV           1
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
 /* LED */
 #define CONFIG_AT91_LED
 /*
  * BOOTP options
  */
-#define CONFIG_BOOTP_BOOTFILESIZE      1
-#define CONFIG_BOOTP_BOOTPATH          1
-#define CONFIG_BOOTP_GATEWAY           1
-#define CONFIG_BOOTP_HOSTNAME          1
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
 
 /*
  * Command line configuration.
 #undef CONFIG_CMD_LOADS
 #undef CONFIG_CMD_SOURCE
 
-#define CONFIG_CMD_PING                1
-#define CONFIG_CMD_DHCP                1
-#define CONFIG_CMD_NAND                1
-#define CONFIG_CMD_USB         1
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
 
 /* SDRAM */
 #define CONFIG_NR_DRAM_BANKS           1
-#define PHYS_SDRAM                     0x20000000
-#define PHYS_SDRAM_SIZE                        0x04000000      /* 64 megs */
+#define CONFIG_SYS_SDRAM_BASE          0x20000000
+#define CONFIG_SYS_SDRAM_SIZE          0x04000000
+#define CONFIG_SYS_INIT_SP_ADDR \
+       (ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE)
 
 /* DataFlash */
 #define CONFIG_ATMEL_DATAFLASH_SPI
-#define CONFIG_HAS_DATAFLASH           1
+#define CONFIG_HAS_DATAFLASH
 #define CONFIG_SYS_SPI_WRITE_TOUT              (5*CONFIG_SYS_HZ)
 #define CONFIG_SYS_MAX_DATAFLASH_BANKS         2
 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0    0xC0000000      /* CS0 */
 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3    0xD0000000      /* CS3 */
-#define AT91_SPI_CLK                   15000000
-#define DATAFLASH_TCSS                 (0x1a << 16)
-#define DATAFLASH_TCHS                 (0x1 << 24)
+#define AT91_SPI_CLK                           15000000
+#define DATAFLASH_TCSS                         (0x1a << 16)
+#define DATAFLASH_TCHS                         (0x1 << 24)
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_NAND_ATMEL
 #define CONFIG_SYS_MAX_NAND_DEVICE             1
 #define CONFIG_SYS_NAND_BASE                   0x40000000
-#define CONFIG_SYS_NAND_DBW_8                  1
+#define CONFIG_SYS_NAND_DBW_8
 /* our ALE is AD22 */
 #define CONFIG_SYS_NAND_MASK_ALE               (1 << 22)
 /* our CLE is AD21 */
 #endif
 
 /* NOR flash - no real flash on this board */
-#define CONFIG_SYS_NO_FLASH                    1
+#define CONFIG_SYS_NO_FLASH
 
 /* Ethernet */
-#define CONFIG_NET_MULTI               1
-#define CONFIG_DRIVER_DM9000           1
+#define CONFIG_NET_MULTI
+#define CONFIG_DRIVER_DM9000
 #define CONFIG_DM9000_BASE             0x30000000
 #define DM9000_IO                      CONFIG_DM9000_BASE
 #define DM9000_DATA                    (CONFIG_DM9000_BASE + 4)
-#define CONFIG_DM9000_USE_16BIT                1
-#define CONFIG_DM9000_NO_SROM          1
+#define CONFIG_DM9000_USE_16BIT
+#define CONFIG_DM9000_NO_SROM
 #define CONFIG_NET_RETRY_COUNT         20
-#define CONFIG_RESET_PHY_R             1
+#define CONFIG_RESET_PHY_R
 
 /* USB */
 #define CONFIG_USB_ATMEL
-#define CONFIG_USB_OHCI_NEW            1
-#define CONFIG_DOS_PARTITION           1
-#define CONFIG_SYS_USB_OHCI_CPU_INIT           1
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
 #define CONFIG_SYS_USB_OHCI_REGS_BASE          0x00500000      /* AT91SAM9261_UHP_BASE */
 #ifdef CONFIG_AT91SAM9G10EK
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME          "at91sam9g10"
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME          "at91sam9261"
 #endif
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     2
-#define CONFIG_USB_STORAGE             1
-#define CONFIG_CMD_FAT                 1
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
 
 #define CONFIG_SYS_LOAD_ADDR                   0x22000000      /* load address */
 
-#define CONFIG_SYS_MEMTEST_START               PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_START               CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END                 0x23e00000
 
 #ifdef CONFIG_SYS_USE_DATAFLASH_CS0
 
 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_ENV_IS_IN_DATAFLASH     1
+#define CONFIG_ENV_IS_IN_DATAFLASH
 #define CONFIG_SYS_MONITOR_BASE        (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
 #define CONFIG_ENV_OFFSET      0x4200
 #define CONFIG_ENV_ADDR                (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 #elif CONFIG_SYS_USE_DATAFLASH_CS3
 
 /* bootstrap + u-boot + env + linux in dataflash on CS3 */
-#define CONFIG_ENV_IS_IN_DATAFLASH     1
+#define CONFIG_ENV_IS_IN_DATAFLASH
 #define CONFIG_SYS_MONITOR_BASE        (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + 0x8400)
 #define CONFIG_ENV_OFFSET      0x4200
 #define CONFIG_ENV_ADDR                (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + CONFIG_ENV_OFFSET)
 #else /* CONFIG_SYS_USE_NANDFLASH */
 
 /* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_IS_IN_NAND  1
+#define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_OFFSET              0x60000
 #define CONFIG_ENV_OFFSET_REDUND       0x80000
 #define CONFIG_ENV_SIZE                0x20000         /* 1 sector = 128 kB */
 
 #endif
 
-#define CONFIG_BAUDRATE                115200
-#define CONFIG_SYS_BAUDRATE_TABLE      {115200 , 19200, 38400, 57600, 9600 }
-
 #define CONFIG_SYS_PROMPT              "U-Boot> "
 #define CONFIG_SYS_CBSIZE              256
 #define CONFIG_SYS_MAXARGS             16
 #define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP            1
-#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
 
 /*
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN          ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
 
-#define CONFIG_STACKSIZE       (32*1024)       /* regular stack */
+#define CONFIG_STACKSIZE               (32*1024)       /* regular stack */
 
 #ifdef CONFIG_USE_IRQ
 #error CONFIG_USE_IRQ not supported