Add more information about DDR timing values and print them in board info

diff --git a/u-boot/board/ar7240/common/common.c b/u-boot/board/ar7240/common/common.c
index 60f76a38a1e958852076f7c85da8228e4a90cbfe..7b71871420318eecfa2f2102178ba04a2d7c0e31 100644 (file)
--- a/u-boot/board/ar7240/common/common.c
+++ b/u-boot/board/ar7240/common/common.c
@@ -122,8 +122,11 @@ void print_board_info(void)
        /* DDR interface width */
        printf("%d-bit ", qca_dram_ddr_width());
 
-       /* CAS latency */
-       printf("CL%d\n", qca_dram_cas_lat());
+       /* tCL-tRCD-tRP-tRAS latency */
+       printf("CL%d-%d-%d-%d\n", qca_dram_cas_lat(),
+                                                         qca_dram_trcd_lat(),
+                                                         qca_dram_trp_lat(),
+                                                         qca_dram_tras_lat());
 
        /* SPI NOR FLASH sizes and types */
        printf("%" ALIGN_SIZE "s ", "FLASH:");

diff --git a/u-boot/cpu/mips/ar7240/qca_dram.c b/u-boot/cpu/mips/ar7240/qca_dram.c
index 3bca1d3e09dcf8ca7bf240604c997c993d77b5ae..cc07897d3c20ed7ccbbd40a6c4e9bd4f956d9d2a 100644 (file)
--- a/u-boot/cpu/mips/ar7240/qca_dram.c
+++ b/u-boot/cpu/mips/ar7240/qca_dram.c
@@ -123,7 +123,7 @@ u32 qca_dram_ddr_width(void)
 /*
  * Returns CAS latency, based on setting in DDR_CONFIG register
  */
-u32 qca_dram_cas_lat(void)
+inline u32 qca_dram_cas_lat(void)
 {
 #ifndef CONFIG_BOARD_DRAM_CAS_LATENCY
        u32 reg;
@@ -141,6 +141,45 @@ u32 qca_dram_cas_lat(void)
 #endif
 }
 
+/*
+ * Returns tRCD latency
+ */
+inline u32 qca_dram_trcd_lat(void)
+{
+       u32 reg;
+
+       reg = (qca_soc_reg_read(QCA_DDR_CFG_REG) & QCA_DDR_CFG_TRCD_MASK)
+                 >> QCA_DDR_CFG_TRCD_SHIFT;
+
+       return reg / 2;
+}
+
+/*
+ * Returns tRP latency
+ */
+inline u32 qca_dram_trp_lat(void)
+{
+       u32 reg;
+
+       reg = (qca_soc_reg_read(QCA_DDR_CFG_REG) & QCA_DDR_CFG_TRP_MASK)
+                 >> QCA_DDR_CFG_TRP_SHIFT;
+
+       return reg / 2;
+}
+
+/*
+ * Returns tRAS latency
+ */
+inline u32 qca_dram_tras_lat(void)
+{
+       u32 reg;
+
+       reg = (qca_soc_reg_read(QCA_DDR_CFG_REG) & QCA_DDR_CFG_TRAS_MASK)
+                 >> QCA_DDR_CFG_TRAS_SHIFT;
+
+       return reg / 2;
+}
+
 /*
  * ===============================================
  * DQS delay tap controller tune related functions

diff --git a/u-boot/include/soc/qca_soc_common.h b/u-boot/include/soc/qca_soc_common.h
index 5a1395fa58a75ee493f0851b4cd31028621d24d4..2abf5d534be5eeadd16c2a363f7a15cff02aff16 100644 (file)
--- a/u-boot/include/soc/qca_soc_common.h
+++ b/u-boot/include/soc/qca_soc_common.h
@@ -1593,9 +1593,12 @@ u32    qca_sf_sfdp_info(u32 bank, u32 *flash_size, u32 *sector_size, u8 *erase_c
 u32    qca_sf_jedec_id(u32 bank);
 u32    qca_dram_type(void);
 u32    qca_dram_size(void);
-u32    qca_dram_cas_lat(void);
 u32    qca_dram_ddr_width(void);
 void   qca_dram_init(void);
+inline u32 qca_dram_cas_lat(void);
+inline u32 qca_dram_trcd_lat(void);
+inline u32 qca_dram_trp_lat(void);
+inline u32 qca_dram_tras_lat(void);
 #endif /* !__ASSEMBLY__ */
 
 /*