Add RTC related registers in QC/A SOC common header file
authorPiotr Dymacz <pepe2k@gmail.com>
Sat, 13 Feb 2016 19:41:27 +0000 (20:41 +0100)
committerPiotr Dymacz <pepe2k@gmail.com>
Sat, 13 Feb 2016 19:41:27 +0000 (20:41 +0100)
u-boot/include/soc/qca_soc_common.h

index 07afd29968ed7a19b095476394193ee62d67a8f3..b01baf8411c9a35c269042ac20d47e18326b4a9a 100644 (file)
 #define QCA_RST_REVISION_ID_MAJOR_QCA953X_V2_VAL       0x0160
 #define QCA_RST_REVISION_ID_MAJOR_QCA9558_VAL          0x1130
 
+/*
+ * RTC registers
+ */
+#define QCA_RTC_RST_CTRL_REG                                   QCA_RTC_BASE_REG + 0x00
+#define QCA_RTC_XTAL_CTRL_REG                                  QCA_RTC_BASE_REG + 0x04
+#define QCA_RTC_WLAN_PLL_CTRL_REG                              QCA_RTC_BASE_REG + 0x14
+#define QCA_RTC_PLL_SETTLE_REG                                 QCA_RTC_BASE_REG + 0x18
+#define QCA_RTC_XTAL_SETTLE_REG                                        QCA_RTC_BASE_REG + 0x1C
+#define QCA_RTC_CLK_OUT_REG                                            QCA_RTC_BASE_REG + 0x20
+#define QCA_RTC_RST_CAUSE_REG                                  QCA_RTC_BASE_REG + 0x28
+#define QCA_RTC_SYS_SLEEP_REG                                  QCA_RTC_BASE_REG + 0x2C
+#define QCA_RTC_KEEP_AWAKE_REG                                 QCA_RTC_BASE_REG + 0x34
+#define QCA_RTC_DERIVED_RTC_CLK_REG                            QCA_RTC_BASE_REG + 0x38
+#define QCA_RTC_PLL_CTRL2_REG                                  QCA_RTC_BASE_REG + 0x3C
+#define QCA_RTC_SYNC_RST_REG                                   QCA_RTC_BASE_REG + 0x40
+#define QCA_RTC_SYNC_STATUS_REG                                        QCA_RTC_BASE_REG + 0x44
+#define QCA_RTC_SYNC_DERIVED_REG                               QCA_RTC_BASE_REG + 0x48
+#define QCA_RTC_FORCE_WAKE_REG                                 QCA_RTC_BASE_REG + 0x4C
+#define QCA_RTC_INTERRUPT_CAUSE_REG                            QCA_RTC_BASE_REG + 0x50
+#define QCA_RTC_INTERRUPT_EN_REG                               QCA_RTC_BASE_REG + 0x54
+#define QCA_RTC_INTERRUPT_MASK_REG                             QCA_RTC_BASE_REG + 0x58
+
+/*
+ * RTC registers BIT fields
+ */
+
+/* RESET_CONTROL register (RTC reset control) */
+#define QCA_RTC_RST_CTRL_MAC_WARM_RST_SHIFT            0
+#define QCA_RTC_RST_CTRL_MAC_WARM_RST_MASK             (1 << QCA_RTC_RST_CTRL_MAC_WARM_RST_SHIFT)
+#define QCA_RTC_RST_CTRL_MAC_COLD_RST_SHIFT            1
+#define QCA_RTC_RST_CTRL_MAC_COLD_RST_MASK             (1 << QCA_RTC_RST_CTRL_MAC_COLD_RST_SHIFT)
+#define QCA_RTC_RST_CTRL_WARM_RST_SHIFT                        2
+#define QCA_RTC_RST_CTRL_WARM_RST_MASK                 (1 << QCA_RTC_RST_CTRL_WARM_RST_SHIFT)
+#define QCA_RTC_RST_CTRL_COLD_RST_SHIFT                        3
+#define QCA_RTC_RST_CTRL_COLD_RST_MASK                 (1 << QCA_RTC_RST_CTRL_COLD_RST_SHIFT)
+
+/* RESET_CAUSE register (Reset cause) */
+#define QCA_RTC_RST_CAUSE_LAST_SHIFT                   0
+#define QCA_RTC_RST_CAUSE_LAST_MASK                            BITS(QCA_RTC_RST_CAUSE_LAST_SHIFT, 2)
+
+#define QCA_RTC_RST_CAUSE_LAST_HARD_VAL                        0
+#define QCA_RTC_RST_CAUSE_LAST_COLD_VAL                        1
+#define QCA_RTC_RST_CAUSE_LAST_WARM_VAL                        2
+
+/* RTC_SYNC_REGISTER register (RTC reset, force sleep and force wakeup) */
+#define QCA_RTC_SYNC_RST_RESET_SHIFT                   0
+#define QCA_RTC_SYNC_RST_RESET_MASK                            (1 << QCA_RTC_SYNC_RST_RESET_SHIFT)
+
+/* RTC_SYNC_STATUS register (RTC sync/sleep status) */
+#define QCA_RTC_SYNC_STATUS_SHUTDOWN_SHIFT             0
+#define QCA_RTC_SYNC_STATUS_SHUTDOWN_MASK              (1 << QCA_RTC_SYNC_STATUS_SHUTDOWN_SHIFT)
+#define QCA_RTC_SYNC_STATUS_ON_SHIFT                   1
+#define QCA_RTC_SYNC_STATUS_ON_MASK                            (1 << QCA_RTC_SYNC_STATUS_ON_SHIFT)
+#define QCA_RTC_SYNC_STATUS_SLEEP_SHIFT                        2
+#define QCA_RTC_SYNC_STATUS_SLEEP_MASK                 (1 << QCA_RTC_SYNC_STATUS_SLEEP_SHIFT)
+#define QCA_RTC_SYNC_STATUS_WAKEUP_SHIFT               3
+#define QCA_RTC_SYNC_STATUS_WAKEUP_MASK                        (1 << QCA_RTC_SYNC_STATUS_WAKEUP_SHIFT)
+#define QCA_RTC_SYNC_STATUS_WRESET_SHIFT               4
+#define QCA_RTC_SYNC_STATUS_WRESET_MASK                        (1 << QCA_RTC_SYNC_STATUS_WRESET_SHIFT)
+#define QCA_RTC_SYNC_STATUS_PLL_CHANGING_SHIFT 5
+#define QCA_RTC_SYNC_STATUS_PLL_CHANGING_MASK  (1 << QCA_RTC_SYNC_STATUS_PLL_CHANGING_SHIFT)
+
 /*
  * SPI serial flash registers
  */