ppc/P1_P2_RDB: NAND Boot Support
authorDipen Dudhat <dipen.dudhat@freescale.com>
Thu, 8 Oct 2009 08:03:18 +0000 (13:33 +0530)
committerKumar Gala <galak@kernel.crashing.org>
Fri, 16 Oct 2009 15:21:39 +0000 (10:21 -0500)
NAND Boot support for P1 and P2 series RDB platforms.

This patch is derived from NAND Boot support on MPC8536DS.

Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
MAKEALL
Makefile
board/freescale/p1_p2_rdb/config.mk
board/freescale/p1_p2_rdb/tlb.c
include/configs/P1_P2_RDB.h
nand_spl/board/freescale/p1_p2_rdb/Makefile [new file with mode: 0644]
nand_spl/board/freescale/p1_p2_rdb/nand_boot.c [new file with mode: 0644]

diff --git a/MAKEALL b/MAKEALL
index 38cd0768dcb1f2b75df0b46d06ed87027df704a1..cfb94725c37a24c8d61835b2609abad9f07d4a71 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -404,9 +404,13 @@ LIST_85xx="                \
        P2020DS         \
        P2020DS_36BIT   \
        P1011RDB        \
+       P1011RDB_NAND   \
        P1020RDB        \
+       P1020RDB_NAND   \
        P2010RDB        \
+       P2010RDB_NAND   \
        P2020RDB        \
+       P2020RDB_NAND   \
        PM854           \
        PM856           \
        sbc8540         \
index 9637643cd5b00b22fe4dbdb2575a864a8cac23a4..b067a4c7b96e5954abccebd80a0e0d3b8175138b 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -2511,9 +2511,13 @@ P2020DS_config:          unconfig
        @$(MKCONFIG) -t $(@:_config=) P2020DS ppc mpc85xx p2020ds freescale
 
 P1011RDB_config        \
+P1011RDB_NAND_config \
 P1020RDB_config        \
+P1020RDB_NAND_config \
 P2010RDB_config \
-P2020RDB_config:       unconfig
+P2010RDB_NAND_config \
+P2020RDB_config \
+P2020RDB_NAND_config:  unconfig
        @$(MKCONFIG) -t $(@:_config=) P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale
 
 PM854_config:  unconfig
index a56b5366b75ffcddfb6440191e5d8a86a185e2fd..17abcf8f779b294d8df29dfa20bf3062aad98484 100644 (file)
 # p1_p2rdb board
 #
 
+ifndef NAND_SPL
+ifeq ($(CONFIG_MK_NAND), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds
+endif
+endif
+
 ifndef TEXT_BASE
 TEXT_BASE = 0xeff80000
 endif
index cf9bffed5f7505dbfc925340d88b44671491a74f..0009913eaa8be77e385d2260fe227ce823bd7d01 100644 (file)
@@ -78,6 +78,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 6, BOOKE_PAGESZ_1M, 1),
 
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+       /* *I*G - L2SRAM */
+       SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 7, BOOKE_PAGESZ_256K, 1),
+       SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+                       CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 8, BOOKE_PAGESZ_256K, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
index 8e97ad068195eda4c5e4ccc49a3764a19fa3659b..aacd4ca852788262644d76353ee7c79b98a076c5 100644 (file)
 #define CONFIG_P2020
 #endif
 
+#ifdef CONFIG_MK_NAND
+#define CONFIG_NAND_U_BOOT             1
+#define CONFIG_RAMBOOT_NAND            1
+#define CONFIG_RAMBOOT_TEXT_BASE       0xf8f82000
+#endif
+
 /* High Level Configuration Options */
 #define CONFIG_BOOKE           1       /* BOOKE */
 #define CONFIG_E500            1       /* BOOKE e500 family */
@@ -82,16 +88,34 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_MEMTEST_END         0x1fffffff
 #define CONFIG_PANIC_HANG      /* do not reset board on panic */
 
+ /*
+  * Config the L2 Cache as L2 SRAM
+  */
+#define CONFIG_SYS_INIT_L2_ADDR                0xf8f80000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS   0xff8f80000ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS   CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE             (512 << 10)
+#define CONFIG_SYS_INIT_L2_END         (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
 #define CONFIG_SYS_CCSRBAR             0xffe00000      /* relocated CCSRBAR */
 #define CONFIG_SYS_CCSRBAR_PHYS        CONFIG_SYS_CCSRBAR      /* physical addr of */
                                                        /* CCSRBAR */
 #define CONFIG_SYS_IMMR                CONFIG_SYS_CCSRBAR      /* PQII uses */
                                                        /* CONFIG_SYS_IMMR */
+
+#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSRBAR_DEFAULT     CONFIG_SYS_CCSRBAR
+#else
+#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
+#endif
+
 #define CONFIG_SYS_PCIE2_ADDR          (CONFIG_SYS_CCSRBAR+0x9000)
 #define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR+0xa000)
 
@@ -158,6 +182,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_SYS_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 
+#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
@@ -177,7 +207,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon*/
 #define CONFIG_SYS_MALLOC_LEN          (1024 * 1024)   /* Reserved for malloc*/
 
+#ifndef CONFIG_NAND_SPL
 #define CONFIG_SYS_NAND_BASE           0xffa00000
+#else
+#define CONFIG_SYS_NAND_BASE           0xfff00000
+#endif
 #define CONFIG_SYS_NAND_BASE_PHYS      CONFIG_SYS_NAND_BASE
 #define CONFIG_SYS_NAND_BASE_LIST      {CONFIG_SYS_NAND_BASE}
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
@@ -187,6 +221,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_NAND_FSL_ELBC           1
 #define CONFIG_SYS_NAND_BLOCK_SIZE     (16 * 1024)
 
+/* NAND boot: 4K NAND loader config */
+#define CONFIG_SYS_NAND_SPL_SIZE       0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE    ((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST     (CONFIG_SYS_INIT_L2_ADDR)
+#define CONFIG_SYS_NAND_U_BOOT_START   (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    (0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC   (CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP                ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+
 /* NAND flash config */
 #define CONFIG_NAND_BR_PRELIM  (CONFIG_SYS_NAND_BASE_PHYS \
                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
@@ -202,10 +245,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
                                | OR_FCM_TRLX \
                                | OR_FCM_EHTR)
 
+#ifdef CONFIG_RAMBOOT_NAND
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
+#else
 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 #define CONFIG_SYS_BR1_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
 #define CONFIG_SYS_OR1_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
+#endif
 
 #define CONFIG_SYS_VSC7385_BASE        0xffb00000
 
@@ -371,14 +421,22 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * Environment
  */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR                0xfff80000
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_NAND)
+       #define CONFIG_ENV_IS_IN_NAND   1
+       #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
+       #define CONFIG_ENV_OFFSET       ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
 #else
-#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+       #define CONFIG_ENV_IS_IN_FLASH  1
+       #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+       #define CONFIG_ENV_ADDR         0xfff80000
+       #else
+       #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+       #endif
+       #define CONFIG_ENV_SIZE         0x2000
+       #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 #endif
-#define CONFIG_ENV_SIZE                0x2000
-#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
 
 #define CONFIG_LOADS_ECHO      1       /* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
diff --git a/nand_spl/board/freescale/p1_p2_rdb/Makefile b/nand_spl/board/freescale/p1_p2_rdb/Makefile
new file mode 100644 (file)
index 0000000..1d5e319
--- /dev/null
@@ -0,0 +1,127 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# Copyright 2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+NAND_SPL := y
+TEXT_BASE := 0xfff00000
+PAD_TO := 0xfff01000
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/cpu/$(CPU)/u-boot-nand_spl.lds
+LDFLAGS        = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS += -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_NAND_SPL
+
+SOBJS  = start.o resetvec.o
+COBJS  = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+         nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
+
+SRCS   := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR  := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj        := $(OBJTREE)/nand_spl/
+
+ALL    = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all:   $(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+       $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin:      $(nandobj)u-boot-spl
+       $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl:  $(OBJS)
+       cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
+               -Map $(nandobj)u-boot-spl.map \
+               -o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+
+$(obj)cache.c:
+       @rm -f $(obj)cache.c
+       ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c
+
+$(obj)cpu_init_early.c:
+       @rm -f $(obj)cpu_init_early.c
+       ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
+
+$(obj)cpu_init_nand.c:
+       @rm -f $(obj)cpu_init_nand.c
+       ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+
+$(obj)fsl_law.c:
+       @rm -f $(obj)fsl_law.c
+       ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+
+$(obj)law.c:
+       @rm -f $(obj)law.c
+       ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
+
+$(obj)nand_boot_fsl_elbc.c:
+       @rm -f $(obj)nand_boot_fsl_elbc.c
+       ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
+              $(obj)nand_boot_fsl_elbc.c
+
+$(obj)ns16550.c:
+       @rm -f $(obj)ns16550.c
+       ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+
+$(obj)resetvec.S:
+       @rm -f $(obj)resetvec.S
+       ln -s $(SRCTREE)/cpu/$(CPU)/resetvec.S $(obj)resetvec.S
+
+$(obj)fixed_ivor.S:
+       @rm -f $(obj)fixed_ivor.S
+       ln -sf $(SRCTREE)/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+
+$(obj)start.S: $(obj)fixed_ivor.S
+       @rm -f $(obj)start.S
+       ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S
+
+$(obj)tlb.c:
+       @rm -f $(obj)tlb.c
+       ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c
+
+$(obj)tlb_table.c:
+       @rm -f $(obj)tlb_table.c
+       ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+
+#########################################################################
+
+$(obj)%.o:     $(obj)%.S
+       $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:     $(obj)%.c
+       $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c
new file mode 100644 (file)
index 0000000..bd513b8
--- /dev/null
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm-ppc/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_law.h>
+
+#define SYSCLK_MASK     0x00200000
+#define BOARDREV_MASK   0x10100000
+#define BOARDREV_B      0x10100000
+#define BOARDREV_C      0x00100000
+
+#define SYSCLK_66       66666666
+#define SYSCLK_50       50000000
+#define SYSCLK_100      100000000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+       uint plat_ratio, bus_clk, sys_clk;
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+       uint val, temp, sysclk_mask;
+
+       val = pgpio->gpdat;
+       sysclk_mask = val & SYSCLK_MASK;
+       temp = val & BOARDREV_MASK;
+       if (temp == BOARDREV_C) {
+               if(sysclk_mask == 0)
+                       sys_clk = SYSCLK_66;
+               else
+                       sys_clk = SYSCLK_100;
+       } else if (temp == BOARDREV_B) {
+               if(sysclk_mask == 0)
+                       sys_clk = SYSCLK_66;
+               else
+                       sys_clk = SYSCLK_50;
+       }
+
+       plat_ratio = gur->porpllsr & 0x0000003e;
+       plat_ratio >>= 1;
+       bus_clk = plat_ratio * sys_clk;
+       NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+                       bus_clk / 16 / CONFIG_BAUDRATE);
+
+       puts("\nNAND boot... ");
+
+       /* copy code to DDR and jump to it - this should not return */
+       /* NOTE - code has to be copied out of NAND buffer before
+        * other blocks can be read.
+        */
+       relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
+                       CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+       nand_boot();
+}
+
+void putc(char c)
+{
+       if (c == '\n')
+               NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+       NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+       while (*str)
+               putc(*str++);
+}