ARM: k2g: add a workaround to reset the phy

This patch adds a workaround to reset the phy one time during boot
using GPIO0 pin 10 to make sure, the Phy latches the configuration
from the input pins correctly.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
index 8b902641ec9ac84cf0add25555451448512cea0f..971c081bb3c3b9303ae05ab3fcacf1162280366f 100644 (file)
--- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
@@ -69,9 +69,12 @@
 
 #define K2G_GPIO0_BASE                 0X02603000
 #define K2G_GPIO1_BASE                 0X0260a000
+#define K2G_GPIO0_BANK0_BASE           K2G_GPIO0_BASE + 0x10
 #define K2G_GPIO1_BANK2_BASE           K2G_GPIO1_BASE + 0x38
 #define K2G_GPIO_DIR_OFFSET            0x0
+#define K2G_GPIO_OUTDATA_OFFSET                0x4
 #define K2G_GPIO_SETDATA_OFFSET                0x8
+#define K2G_GPIO_CLRDATA_OFFSET                0xC
 
 /* BOOTCFG RESETMUX8 */
 #define KS2_RSTMUX8                    (KS2_DEVICE_STATE_CTRL_BASE + 0x328)

diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index 39a782e47960ee13412e2864cdef788c8d5b3c9c..6d0fc21c67acc29f05b411fd608633a327ed0de4 100644 (file)
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -315,6 +315,21 @@ int embedded_dtb_select(void)
                             BIT(9));
                setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
                             BIT(9));
+       } else if (board_is_k2g_ice()) {
+               /* GBE Phy workaround. For Phy to latch the input
+                * configuration, a GPIO reset is asserted at the
+                * Phy reset pin to latch configuration correctly after SoC
+                * reset. GPIO0 Pin 10 (Ball AA20) is used for this on ICE
+                * board. Just do a low to high transition.
+                */
+               clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET,
+                            BIT(10));
+               setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET,
+                            BIT(10));
+               /* Delay just to get a transition to high */
+               udelay(100);
+               setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET,
+                            BIT(10));
        }
 
        return 0;