imx: imx7d: fix ahb clock mux 1

The clock parent of the AHB root clock when using mux option 1
is the SYS PLL 270MHz clock. This is specified in  Table 5-11
Clock Root Table of the i.MX 7Dual Applications Processor
Reference Manual.

While it could be a documentation error, the 270MHz parent is
also mentioned in the boot ROM configuration in Table 6-28: The
clock is by default at 135MHz due to a POST_PODF value of 1
(=> divider of 2).

Signed-off-by: Stefan Agner <stefan@agner.ch>

diff --git a/arch/arm/cpu/armv7/mx7/clock_slice.c b/arch/arm/cpu/armv7/mx7/clock_slice.c
index ad5d504d28ef0ccd19af89a37d6ab42092d6db83..1665df92adc82df91237401a4e4948f4f3434504 100644 (file)
--- a/arch/arm/cpu/armv7/mx7/clock_slice.c
+++ b/arch/arm/cpu/armv7/mx7/clock_slice.c
@@ -55,7 +55,7 @@ static struct clk_root_map root_array[] = {
          PLL_ENET_MAIN_250M_CLK, PLL_AUDIO_MAIN_CLK}
        },
        {AHB_CLK_ROOT, CCM_AHB_CHANNEL,
-        {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK,
+        {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
          PLL_SYS_PFD0_392M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
          PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
        },