tegra: Correct tegra124 clock name
authorSimon Glass <sjg@chromium.org>
Mon, 1 Apr 2019 20:38:38 +0000 (13:38 -0700)
committerTom Warren <twarren@nvidia.com>
Fri, 24 May 2019 17:13:12 +0000 (10:13 -0700)
The first clock type appears to have and incorrect setting for out of the
mux outputs. It should be CLK_M, not OSC. Fix it and its only user.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
arch/arm/mach-tegra/tegra124/clock.c
board/nvidia/nyan-big/nyan-big.c

index 3bd6cf2afff6734eead4e6c4eccb99fc6719afac..70916ea3c1872a207c8a2125491b70e446eff679 100644 (file)
@@ -71,7 +71,7 @@ enum {
  */
 #define CLK(x) CLOCK_ID_ ## x
 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
-       { CLK(AUDIO),   CLK(XCPU),      CLK(PERIPH),    CLK(OSC),
+       { CLK(AUDIO),   CLK(XCPU),      CLK(PERIPH),    CLK(CLK_M),
                CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
                MASK_BITS_31_30},
        { CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(AUDIO),
index ff5c67de98542a82ef04933496db123f32024ea6..3c7bfead249ff756fc309abfa199688ca19df12a 100644 (file)
@@ -121,7 +121,7 @@ static void enable_required_clocks(void)
 int nvidia_board_init(void)
 {
        clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000);
-       clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_OSC, 1500000);
+       clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_CLK_M, 1500000);
 
        /* For external MAX98090 audio codec */
        clock_external_output(1);