imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
-#ifdef CONFIG_VIDEO
+ #ifdef CONFIG_FSL_ESDHC_IMX
+ struct fsl_esdhc_cfg esdhc_cfg = {
+ MMC_SDHC1_BASE_ADDR,
+ };
+
+ int board_mmc_getcd(struct mmc *mmc)
+ {
+ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
+ gpio_direction_input(IMX_GPIO_NR(1, 1));
+
+ return !gpio_get_value(IMX_GPIO_NR(1, 1));
+ }
+
+ #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+ #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH)
+
+ int board_mmc_init(bd_t *bis)
+ {
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+ };
+
+ esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
+
+ return fsl_esdhc_initialize(bis, &esdhc_cfg);
+ }
+ #endif
+
static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
{
static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;