efi_status_t reset_status,
unsigned long data_size, void *reset_data)
{
- switch (reset_type) {
- case EFI_RESET_COLD:
- case EFI_RESET_WARM:
- case EFI_RESET_PLATFORM_SPECIFIC:
+ if (reset_type == EFI_RESET_COLD ||
+ reset_type == EFI_RESET_WARM ||
+ reset_type == EFI_RESET_PLATFORM_SPECIFIC) {
psci_system_reset();
- break;
- case EFI_RESET_SHUTDOWN:
+ } else if (reset_type == EFI_RESET_SHUTDOWN) {
psci_system_off();
- break;
}
while (1) { }
{
u32 data;
u32 value_local = value;
+ int ret;
+
+ ret = zynqmp_mmio_read(address, &data);
+ if (ret)
+ return ret;
- zynqmp_mmio_read(address, &data);
data &= ~mask;
value_local &= mask;
value_local |= data;
zynq-zturn.dtb \
zynq-zybo.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
- zynqmp-mini-emmc.dtb \
+ zynqmp-mini-emmc0.dtb \
+ zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb \
zynqmp-zcu100-revC.dtb \
zynqmp-zcu102-revA.dtb \
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
autorepeat;
sw14 {
label = "sw14";
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
autorepeat;
K1 {
label = "K1";
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * dts file for Xilinx ZynqMP Mini Configuration
- *
- * (C) Copyright 2018, Xilinx, Inc.
- *
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
- */
-
-/dts-v1/;
-
-/ {
- model = "ZynqMP MINI EMMC";
- compatible = "xlnx,zynqmp";
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- serial0 = &dcc;
- mmc0 = &sdhci0;
- mmc1 = &sdhci1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x20000000>;
- };
-
- dcc: dcc {
- compatible = "arm,dcc";
- status = "disabled";
- u-boot,dm-pre-reloc;
- };
-
- amba: amba {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- sdhci0: sdhci@ff160000 {
- u-boot,dm-pre-reloc;
- compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
- status = "disabled";
- reg = <0x0 0xff160000 0x0 0x1000>;
- clock-names = "clk_xin", "clk_ahb";
- xlnx,device_id = <0>;
- };
-
- sdhci1: sdhci@ff170000 {
- u-boot,dm-pre-reloc;
- compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
- status = "disabled";
- reg = <0x0 0xff170000 0x0 0x1000>;
- clock-names = "clk_xin", "clk_ahb";
- xlnx,device_id = <1>;
- };
- };
-};
-
-&dcc {
- status = "okay";
-};
-
-&sdhci0 {
- status = "okay";
-};
-
-&sdhci1 {
- status = "okay";
-};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP Mini Configuration
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ */
+
+/dts-v1/;
+
+/ {
+ model = "ZynqMP MINI EMMC";
+ compatible = "xlnx,zynqmp";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &dcc;
+ mmc0 = &sdhci0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x20000000>;
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ clk_xin: clk_xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ amba: amba {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ sdhci0: sdhci@ff160000 {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
+ status = "disabled";
+ reg = <0x0 0xff160000 0x0 0x1000>;
+ clock-names = "clk_xin", "clk_ahb";
+ xlnx,device_id = <0>;
+ };
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&sdhci0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP Mini Configuration
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ */
+
+/dts-v1/;
+
+/ {
+ model = "ZynqMP MINI EMMC";
+ compatible = "xlnx,zynqmp";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &dcc;
+ mmc0 = &sdhci1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x20000000>;
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ clk_xin: clk_xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ amba: amba {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ sdhci1: sdhci@ff170000 {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
+ status = "disabled";
+ reg = <0x0 0xff170000 0x0 0x1000>;
+ clock-names = "clk_xin", "clk_xin";
+ xlnx,device_id = <1>;
+ };
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&sdhci1 {
+ status = "okay";
+};
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
autorepeat;
sw4 {
label = "sw4";
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
autorepeat;
sw19 {
label = "sw19";
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
autorepeat;
sw19 {
label = "sw19";
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
autorepeat;
sw19 {
label = "sw19";
{
u32 val;
- switch (reset_type) {
- case EFI_RESET_COLD:
- case EFI_RESET_WARM:
- case EFI_RESET_PLATFORM_SPECIFIC:
+ if (reset_type == EFI_RESET_COLD ||
+ reset_type == EFI_RESET_WARM ||
+ reset_type == EFI_RESET_PLATFORM_SPECIFIC) {
reset_cpu(0);
- break;
- case EFI_RESET_SHUTDOWN:
+ } else if (reset_type == EFI_RESET_SHUTDOWN) {
/*
* We set the watchdog hard reset bit here to distinguish this reset
* from the normal (full) reset. bootcode.bin will not reboot after a
val |= BCM2835_WDOG_RSTS_RASPBERRYPI_HALT;
writel(val, &wdog_regs->rsts);
reset_cpu(0);
- break;
}
while (1) { }
#include <fdtdec.h>
#include <fpga.h>
#include <mmc.h>
+#include <watchdog.h>
#include <wdt.h>
#include <zynqpl.h>
#include <asm/arch/hardware.h>
new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
bootseq_len);
+ if (!new_targets)
+ return -ENOMEM;
if (bootseq >= 0)
sprintf(new_targets, "%s%x %s", mode, bootseq,
{
struct efi_loaded_image loaded_image_info = {};
struct efi_object loaded_image_info_obj = {};
+ struct efi_object mem_obj = {};
struct efi_device_path *memdp = NULL;
efi_status_t ret;
/* actual addresses filled in after efi_load_pe() */
memdp = efi_dp_from_mem(0, 0, 0);
device_path = image_path = memdp;
+ efi_add_handle(&mem_obj);
+
+ ret = efi_add_protocol(mem_obj.handle, &efi_guid_device_path,
+ device_path);
+ if (ret != EFI_SUCCESS)
+ goto exit;
} else {
assert(device_path && image_path);
}
exit:
/* image has returned, loaded-image obj goes *poof*: */
list_del(&loaded_image_info_obj.link);
+ if (mem_obj.handle)
+ list_del(&mem_obj.link);
return ret;
}
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x10000
+# CONFIG_CMD_ZYNQMP is not set
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc0"
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=-1
+CONFIG_SUPPORT_RAW_INITRD=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+# CONFIG_CMDLINE_EDITING is not set
+# CONFIG_AUTO_COMPLETE is not set
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_DM is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+# CONFIG_NET is not set
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+# CONFIG_EFI_LOADER is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x10000
+# CONFIG_CMD_ZYNQMP is not set
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc1"
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=-1
+CONFIG_SUPPORT_RAW_INITRD=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+# CONFIG_CMDLINE_EDITING is not set
+# CONFIG_AUTO_COMPLETE is not set
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_DM is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+# CONFIG_NET is not set
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+# CONFIG_EFI_LOADER is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_TEXT_BASE=0x10000
-# CONFIG_CMD_ZYNQMP is not set
-CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc"
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=-1
-CONFIG_SUPPORT_RAW_INITRD=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="ZynqMP> "
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
-# CONFIG_CMD_BOOTI is not set
-# CONFIG_CMD_GO is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_IMPORTENV is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_CRC32 is not set
-# CONFIG_CMD_DM is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_EMBED=y
-# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
-# CONFIG_DM_DEVICE_REMOVE is not set
-CONFIG_DM_MMC=y
-CONFIG_MMC_SDHCI=y
-# CONFIG_EFI_LOADER is not set
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-r5"
CONFIG_DEBUG_UART=y
+CONFIG_BOOTSTAGE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="ZynqMP r5> "
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_EMBED=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_SDRAM=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_SDRAM=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_SDRAM=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIME=y
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * GUID for basic data partions.
+ */
+static const efi_guid_t partition_basic_data_guid = PARTITION_BASIC_DATA_GUID;
+
#ifdef CONFIG_HAVE_BLOCK_DEVICE
/**
* efi_crc32() - EFI version of crc32 function
} else {
/* default partition type GUID */
memcpy(bin_type_guid,
- &PARTITION_BASIC_DATA_GUID, 16);
+ &partition_basic_data_guid, 16);
}
#else
/* partition type GUID */
memcpy(gpt_e[i].partition_type_guid.b,
- &PARTITION_BASIC_DATA_GUID, 16);
+ &partition_basic_data_guid, 16);
#endif
#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
struct zynq_platform_data {
const char *label;
u16 ngpio;
- int max_bank;
- int bank_min[ZYNQMP_GPIO_MAX_BANK];
- int bank_max[ZYNQMP_GPIO_MAX_BANK];
+ u32 max_bank;
+ u32 bank_min[ZYNQMP_GPIO_MAX_BANK];
+ u32 bank_max[ZYNQMP_GPIO_MAX_BANK];
};
static const struct zynq_platform_data zynqmp_gpio_def = {
struct udevice *dev)
{
struct zynq_gpio_privdata *priv = dev_get_priv(dev);
- int bank;
+ u32 bank;
for (bank = 0; bank < priv->p_data->max_bank; bank++) {
if ((pin_num >= priv->p_data->bank_min[bank]) &&
{
struct zynq_gpio_privdata *priv = dev_get_priv(dev);
- return (gpio >= 0) && (gpio < priv->p_data->ngpio);
+ return gpio < priv->p_data->ngpio;
}
static int check_gpio(unsigned gpio, struct udevice *dev)
/* We shouldn't wait for data inihibit for stop commands, even
though they might use busy signaling */
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
- cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
- cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
+ ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
mask &= ~SDHCI_DATA_INHIBIT;
while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
mask = SDHCI_INT_RESPONSE;
- if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
- cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
+ if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
mask = SDHCI_INT_DATA_AVAIL;
if (!(cmd->resp_type & MMC_RSP_PRESENT))
u32 ctrl;
struct sdhci_host *host;
struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
- u8 tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
+ char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
u8 deviceid;
debug("%s\n", __func__);
#include <linux/compiler.h>
#include <serial.h>
-#define ZYNQ_UART_SR_TXEMPTY (1 << 3) /* TX FIFO empty */
-#define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */
-#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
+DECLARE_GLOBAL_DATA_PTR;
-#define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */
-#define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */
-#define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */
-#define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */
+#define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */
+#define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */
+#define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */
+
+#define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */
+#define ZYNQ_UART_CR_RX_EN BIT(2) /* RX enabled */
+#define ZYNQ_UART_CR_TXRST BIT(1) /* TX logic reset */
+#define ZYNQ_UART_CR_RXRST BIT(0) /* RX logic reset */
#define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
{
- if (!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXEMPTY))
+ if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL)
return -EAGAIN;
writel(c, ®s->tx_rx_fifo);
return 0;
}
-int zynq_serial_setbrg(struct udevice *dev, int baudrate)
+static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
{
struct zynq_uart_priv *priv = dev_get_priv(dev);
unsigned long clock;
{
struct zynq_uart_priv *priv = dev_get_priv(dev);
+ /* No need to reinitialize the UART after relocation */
+ if (gd->flags & GD_FLG_RELOC)
+ return 0;
+
_uart_zynq_serial_init(priv->regs);
return 0;
struct cadence_ttc_regs *regs;
};
+#if CONFIG_IS_ENABLED(BOOTSTAGE)
+ulong timer_get_boot_us(void)
+{
+ u64 ticks = 0;
+ u32 rate = 1;
+ u64 us;
+ int ret;
+
+ ret = dm_timer_init();
+ if (!ret) {
+ /* The timer is available */
+ rate = timer_get_rate(gd->timer);
+ timer_get_count(gd->timer, &ticks);
+ } else {
+ return 0;
+ }
+
+ us = (ticks * 1000) / rate;
+ return us;
+}
+#endif
+
static int cadence_ttc_get_count(struct udevice *dev, u64 *count)
{
struct cadence_ttc_priv *priv = dev_get_priv(dev);
#define CONFIG_ZYNQ_EEPROM_BUS 5
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54
+#define CONFIG_SPD_EEPROM
+#define CONFIG_DDR_SPD
+
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZCU102_H */
typedef void *efi_handle_t;
#define EFI_GUID(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
- ((efi_guid_t) \
{{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, \
((a) >> 24) & 0xff, \
(b) & 0xff, ((b) >> 8) & 0xff, \
(c) & 0xff, ((c) >> 8) & 0xff, \
- (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } })
+ (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } }
/* Generic EFI table header */
struct efi_table_hdr {
#define IMAGE_REL_BASED_MIPS_JMPADDR 5
#define IMAGE_REL_BASED_ARM_MOV32A 5 /* yes, 5 too */
#define IMAGE_REL_BASED_ARM_MOV32 5 /* yes, 5 too */
+#define IMAGE_REL_BASED_RISCV_HI20 5 /* yes, 5 too */
#define IMAGE_REL_BASED_SECTION 6
#define IMAGE_REL_BASED_REL 7
#define IMAGE_REL_BASED_ARM_MOV32T 7 /* yes, 7 too */
#define IMAGE_REL_BASED_THUMB_MOV32 7 /* yes, 7 too */
+#define IMAGE_REL_BASED_RISCV_LOW12I 7 /* yes, 7 too */
+#define IMAGE_REL_BASED_RISCV_LOW12S 8
#define IMAGE_REL_BASED_MIPS_JMPADDR16 9
#define IMAGE_REL_BASED_IA64_IMM64 9 /* yes, 9 too */
#define IMAGE_REL_BASED_DIR64 10
case IMAGE_REL_BASED_DIR64:
*x64 += (uint64_t)delta;
break;
+#ifdef __riscv
+ case IMAGE_REL_BASED_RISCV_HI20:
+ *x32 = ((*x32 & 0xfffff000) + (uint32_t)delta) |
+ (*x32 & 0x00000fff);
+ break;
+ case IMAGE_REL_BASED_RISCV_LOW12I:
+ case IMAGE_REL_BASED_RISCV_LOW12S:
+ /* We know that we're 4k aligned */
+ if (delta & 0xfff) {
+ printf("Unsupported reloc offset\n");
+ return EFI_LOAD_ERROR;
+ }
+ break;
+#endif
default:
printf("Unknown Relocation off %x type %x\n",
offset, type);
static efi_status_t __efi_runtime EFIAPI efi_device_error(void);
static efi_status_t __efi_runtime EFIAPI efi_invalid_parameter(void);
+/*
+ * TODO(sjg@chromium.org): These defines and structs should come from the elf
+ * header for each arch (or a generic header) rather than being repeated here.
+ */
#if defined(CONFIG_ARM64)
#define R_RELATIVE 1027
#define R_MASK 0xffffffffULL
EFI_LDS_PATH = $(srctree)/arch/$(ARCH)/lib/$(EFI_LDS)
-$(obj)/%_efi.so: $(obj)/%.o arch/$(ARCH)/lib/$(EFI_CRT0) \
- arch/$(ARCH)/lib/$(EFI_RELOC)
+$(obj)/efi_crt0.o: $(srctree)/arch/$(ARCH)/lib/$(EFI_CRT0:.o=.S)
+ $(call if_changed_dep,as_o_S)
+
+$(obj)/efi_reloc.o: $(srctree)/arch/$(ARCH)/lib/$(EFI_RELOC:.o=.c) $(recordmcount_source) FORCE
+ $(call cmd,force_checksrc)
+ $(call if_changed_rule,cc_o_c)
+
+$(obj)/%_efi.so: $(obj)/%.o $(obj)/efi_crt0.o $(obj)/efi_reloc.o
$(call cmd,efi_ld)
# ACPI
MKIMAGEFLAGS_boot.bin = -T zynqimage -R $(srctree)/$(CONFIG_BOOT_INIT_FILE)
endif
ifdef CONFIG_ARCH_ZYNQMP
+ifneq ($(CONFIG_PMUFW_INIT_FILE),"")
+spl/boot.bin: zynqmp-check-pmufw
+zynqmp-check-pmufw: FORCE
+ ( cd $(srctree) && test -r $(CONFIG_PMUFW_INIT_FILE) ) \
+ || ( echo "Cannot read $(CONFIG_PMUFW_INIT_FILE)" && false )
+endif
MKIMAGEFLAGS_boot.bin = -T zynqmpimage -R $(srctree)/$(CONFIG_BOOT_INIT_FILE) \
- -n $(srctree)/$(CONFIG_PMUFW_INIT_FILE)
+ -n "$(shell cd $(srctree); readlink -f $(CONFIG_PMUFW_INIT_FILE))"
endif
spl/boot.bin: $(obj)/u-boot-spl.bin FORCE