mips: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot

Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index 952c57afd7136cb14035b889fa9ad48713d2b154..42af9def69a9572424711c5a00556cd5803cda7a 100644 (file)
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -60,8 +60,8 @@
                sp, sp, GD_SIZE         # reserve space for gd
        and     sp, sp, t0              # force 16 byte alignment
        move    k0, sp                  # save gd pointer
-#ifdef CONFIG_SYS_MALLOC_F_LEN
-       li      t2, CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+       li      t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
        PTR_SUBU \
                sp, sp, t2              # reserve space for early malloc
        and     sp, sp, t0              # force 16 byte alignment
@@ -75,7 +75,7 @@
        blt     t0, t1, 1b
         PTR_ADDIU t0, PTRSIZE
 
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
        PTR_S   sp, GD_MALLOC_BASE(k0)  # gd->malloc_base offset
 #endif
        .endm