arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial support
authorJagan Teki <jagan@amarulasolutions.com>
Sat, 8 Oct 2016 12:30:11 +0000 (18:00 +0530)
committerStefano Babic <sbabic@denx.de>
Wed, 26 Oct 2016 14:53:16 +0000 (16:53 +0200)
Boot Log for i.CoreM6 DualLite/Solo Starter Kit:
-----------------------------------------------

U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46)
Trying to boot from MMC1

U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530)

CPU:   Freescale i.MX6SOLO rev1.3 at 792MHz
CPU:   Industrial temperature grade (-40C to 105C) at 31C
Reset cause: POR
DRAM:  256 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc0 is current device
switch to partitions #0, OK
mmc0 is current device
reading boot.scr
** Unable to read file boot.scr **
reading zImage
6741808 bytes read in 341 ms (18.9 MiB/s)
Booting from mmc ...
reading imx6dl-icore.dtb
30600 bytes read in 19 ms (1.5 MiB/s)
   Booting using the fdt blob at 0x18000000
   Using Device Tree in place at 18000000, end 1800a787

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0

Boot Log for i.CoreM6 Quad/Dual Starter Kit:
--------------------------------------------

U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46)
Trying to boot from MMC1

U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530)

CPU:   Freescale i.MX6Q rev1.2 at 792MHz
CPU:   Industrial temperature grade (-40C to 105C) at 28C
Reset cause: POR
DRAM:  512 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0
icorem6qdl>

Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
arch/arm/cpu/armv7/mx6/Kconfig
arch/arm/include/asm/imx-common/sys_proto.h
board/engicam/icorem6/Kconfig [new file with mode: 0644]
board/engicam/icorem6/MAINTAINERS [new file with mode: 0644]
board/engicam/icorem6/Makefile [new file with mode: 0644]
board/engicam/icorem6/README [new file with mode: 0644]
board/engicam/icorem6/icorem6.c [new file with mode: 0644]
configs/imx6qdl_icore_mmc_defconfig [new file with mode: 0644]
include/configs/imx6qdl_icore.h [new file with mode: 0644]

index d851b264ead09bdf5de6f40c680c4249313b1e3e..5d549bd0bff7a4460851b776b698a926948c9616 100644 (file)
@@ -95,6 +95,13 @@ config TARGET_MX6CUBOXI
 config TARGET_MX6QARM2
        bool "mx6qarm2"
 
+config TARGET_MX6Q_ICORE
+       bool "Support Engicam i.Core"
+       select MX6QDL
+       select DM
+       select DM_THERMAL
+       select SUPPORT_SPL
+
 config TARGET_MX6QSABREAUTO
        bool "mx6qsabreauto"
        select DM
@@ -225,6 +232,7 @@ source "board/compulab/cm_fx6/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"
 source "board/el/el6x/Kconfig"
 source "board/embest/mx6boards/Kconfig"
+source "board/engicam/icorem6/Kconfig"
 source "board/freescale/mx6qarm2/Kconfig"
 source "board/freescale/mx6qsabreauto/Kconfig"
 source "board/freescale/mx6sabresd/Kconfig"
index 6ace8bb512d768226f68a2303c9cb2ddccc46c5a..005435aba1800c673bc9ac89e47dec76e39cc2bb 100644 (file)
 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
 #define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
+#define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL))
 #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
 #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
+#define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
 #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
 #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
 
diff --git a/board/engicam/icorem6/Kconfig b/board/engicam/icorem6/Kconfig
new file mode 100644 (file)
index 0000000..6d62f0e
--- /dev/null
@@ -0,0 +1,12 @@
+if TARGET_MX6Q_ICORE
+
+config SYS_BOARD
+       default "icorem6"
+
+config SYS_VENDOR
+       default "engicam"
+
+config SYS_CONFIG_NAME
+       default "imx6qdl_icore"
+
+endif
diff --git a/board/engicam/icorem6/MAINTAINERS b/board/engicam/icorem6/MAINTAINERS
new file mode 100644 (file)
index 0000000..3e06c6b
--- /dev/null
@@ -0,0 +1,6 @@
+ICOREM6QDL BOARD
+M:     Jagan Teki <jagan@amarulasolutions.com>
+S:     Maintained
+F:     board/engicam/icorem6
+F:     include/configs/icorem6qdl.h
+F:     configs/icorem6qdl_defconfig
diff --git a/board/engicam/icorem6/Makefile b/board/engicam/icorem6/Makefile
new file mode 100644 (file)
index 0000000..9ec9ecd
--- /dev/null
@@ -0,0 +1,6 @@
+# Copyright (C) 2016 Amarula Solutions B.V.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  := icorem6.o
diff --git a/board/engicam/icorem6/README b/board/engicam/icorem6/README
new file mode 100644 (file)
index 0000000..cf2eff2
--- /dev/null
@@ -0,0 +1,31 @@
+How to use U-Boot on Engicam i.CoreM6 DualLite/Solo and Quad/Dual Starter Kit:
+-----------------------------------------------------------------------------
+
+- Build U-Boot for Engicam i.CoreM6 QDL:
+
+$ make mrproper
+$ make icorem6qdl_mmc_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+MMC Boot: JM3 Closed
+
+- Connect the Serial cable between the Starter Kit and the PC for the console.
+(J28 is the Linux Serial console connector)
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
+
+- Note: For loading Linux on Quad/Dual modules set the dtb as
+  icorem6qdl> setenv fdt_file imx6q-icore.dtb
diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
new file mode 100644 (file)
index 0000000..1856972
--- /dev/null
@@ -0,0 +1,400 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/iomux-v3.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
+       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+       PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
+       PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
+       PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+       IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+       IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+       IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+       IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
+};
+
+#ifdef CONFIG_FSL_ESDHC
+#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
+
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+       {USDHC1_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+       int ret = 0;
+
+       switch (cfg->esdhc_base) {
+       case USDHC1_BASE_ADDR:
+               ret = !gpio_get_value(USDHC1_CD_GPIO);
+               break;
+       }
+
+       return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+       int i, ret;
+
+       /*
+       * According to the board_mmc_init() the following map is done:
+       * (U-boot device node)    (Physical Port)
+       * mmc0                          USDHC1
+       */
+       for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+               switch (i) {
+               case 0:
+                       SETUP_IOMUX_PADS(usdhc1_pads);
+                       gpio_direction_input(USDHC1_CD_GPIO);
+                       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+                       break;
+               default:
+                       printf("Warning - USDHC%d controller not supporting\n",
+                              i + 1);
+                       return 0;
+               }
+
+               ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+               if (ret) {
+                       printf("Warning: failed to initialize mmc dev %d\n", i);
+                       return ret;
+               }
+       }
+
+       return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+       SETUP_IOMUX_PADS(uart4_pads);
+
+       return 0;
+}
+
+int board_init(void)
+{
+       /* Address of boot parameters */
+       gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+       return 0;
+}
+
+int dram_init(void)
+{
+       gd->ram_size = imx_ddr_size();
+
+       return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <libfdt.h>
+#include <spl.h>
+
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-ddr.h>
+
+/*
+ * Driving strength:
+ *   0x30 == 40 Ohm
+ *   0x28 == 48 Ohm
+ */
+
+#define IMX6DQ_DRIVE_STRENGTH          0x30
+#define IMX6SDL_DRIVE_STRENGTH         0x28
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+       .dram_sdqs0 = 0x28,
+       .dram_sdqs1 = 0x28,
+       .dram_sdqs2 = 0x28,
+       .dram_sdqs3 = 0x28,
+       .dram_sdqs4 = 0x28,
+       .dram_sdqs5 = 0x28,
+       .dram_sdqs6 = 0x28,
+       .dram_sdqs7 = 0x28,
+       .dram_dqm0 = 0x28,
+       .dram_dqm1 = 0x28,
+       .dram_dqm2 = 0x28,
+       .dram_dqm3 = 0x28,
+       .dram_dqm4 = 0x28,
+       .dram_dqm5 = 0x28,
+       .dram_dqm6 = 0x28,
+       .dram_dqm7 = 0x28,
+       .dram_cas = 0x30,
+       .dram_ras = 0x30,
+       .dram_sdclk_0 = 0x30,
+       .dram_sdclk_1 = 0x30,
+       .dram_reset = 0x30,
+       .dram_sdcke0 = 0x3000,
+       .dram_sdcke1 = 0x3000,
+       .dram_sdba2 = 0x00000000,
+       .dram_sdodt0 = 0x30,
+       .dram_sdodt1 = 0x30,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+       .grp_b0ds = 0x30,
+       .grp_b1ds = 0x30,
+       .grp_b2ds = 0x30,
+       .grp_b3ds = 0x30,
+       .grp_b4ds = 0x30,
+       .grp_b5ds = 0x30,
+       .grp_b6ds = 0x30,
+       .grp_b7ds = 0x30,
+       .grp_addds = 0x30,
+       .grp_ddrmode_ctl = 0x00020000,
+       .grp_ddrpke = 0x00000000,
+       .grp_ddrmode = 0x00020000,
+       .grp_ctlds = 0x30,
+       .grp_ddr_type = 0x000c0000,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+       .dram_sdclk_0 = 0x30,
+       .dram_sdclk_1 = 0x30,
+       .dram_cas = 0x30,
+       .dram_ras = 0x30,
+       .dram_reset = 0x30,
+       .dram_sdcke0 = 0x30,
+       .dram_sdcke1 = 0x30,
+       .dram_sdba2 = 0x00000000,
+       .dram_sdodt0 = 0x30,
+       .dram_sdodt1 = 0x30,
+       .dram_sdqs0 = 0x28,
+       .dram_sdqs1 = 0x28,
+       .dram_sdqs2 = 0x28,
+       .dram_sdqs3 = 0x28,
+       .dram_sdqs4 = 0x28,
+       .dram_sdqs5 = 0x28,
+       .dram_sdqs6 = 0x28,
+       .dram_sdqs7 = 0x28,
+       .dram_dqm0 = 0x28,
+       .dram_dqm1 = 0x28,
+       .dram_dqm2 = 0x28,
+       .dram_dqm3 = 0x28,
+       .dram_dqm4 = 0x28,
+       .dram_dqm5 = 0x28,
+       .dram_dqm6 = 0x28,
+       .dram_dqm7 = 0x28,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+       .grp_ddr_type = 0x000c0000,
+       .grp_ddrmode_ctl = 0x00020000,
+       .grp_ddrpke = 0x00000000,
+       .grp_addds = 0x30,
+       .grp_ctlds = 0x30,
+       .grp_ddrmode = 0x00020000,
+       .grp_b0ds = 0x28,
+       .grp_b1ds = 0x28,
+       .grp_b2ds = 0x28,
+       .grp_b3ds = 0x28,
+       .grp_b4ds = 0x28,
+       .grp_b5ds = 0x28,
+       .grp_b6ds = 0x28,
+       .grp_b7ds = 0x28,
+};
+
+/* mt41j256 */
+static struct mx6_ddr3_cfg mt41j256 = {
+       .mem_speed = 1066,
+       .density = 2,
+       .width = 16,
+       .banks = 8,
+       .rowaddr = 13,
+       .coladdr = 10,
+       .pagesz = 2,
+       .trcd = 1375,
+       .trcmin = 4875,
+       .trasmin = 3500,
+       .SRT = 0,
+};
+
+static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
+       .p0_mpwldectrl0 = 0x000E0009,
+       .p0_mpwldectrl1 = 0x0018000E,
+       .p1_mpwldectrl0 = 0x00000007,
+       .p1_mpwldectrl1 = 0x00000000,
+       .p0_mpdgctrl0 = 0x43280334,
+       .p0_mpdgctrl1 = 0x031C0314,
+       .p1_mpdgctrl0 = 0x4318031C,
+       .p1_mpdgctrl1 = 0x030C0258,
+       .p0_mprddlctl = 0x3E343A40,
+       .p1_mprddlctl = 0x383C3844,
+       .p0_mpwrdlctl = 0x40404440,
+       .p1_mpwrdlctl = 0x4C3E4446,
+};
+
+/* DDR 64bit */
+static struct mx6_ddr_sysinfo mem_q = {
+       .ddr_type       = DDR_TYPE_DDR3,
+       .dsize          = 2,
+       .cs1_mirror     = 0,
+       /* config for full 4GB range so that get_mem_size() works */
+       .cs_density     = 32,
+       .ncs            = 1,
+       .bi_on          = 1,
+       .rtt_nom        = 2,
+       .rtt_wr         = 2,
+       .ralat          = 5,
+       .walat          = 0,
+       .mif3_mode      = 3,
+       .rst_to_cke     = 0x23,
+       .sde_to_rst     = 0x10,
+};
+
+static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
+       .p0_mpwldectrl0 = 0x001F0024,
+       .p0_mpwldectrl1 = 0x00110018,
+       .p1_mpwldectrl0 = 0x001F0024,
+       .p1_mpwldectrl1 = 0x00110018,
+       .p0_mpdgctrl0 = 0x4230022C,
+       .p0_mpdgctrl1 = 0x02180220,
+       .p1_mpdgctrl0 = 0x42440248,
+       .p1_mpdgctrl1 = 0x02300238,
+       .p0_mprddlctl = 0x44444A48,
+       .p1_mprddlctl = 0x46484A42,
+       .p0_mpwrdlctl = 0x38383234,
+       .p1_mpwrdlctl = 0x3C34362E,
+};
+
+/* DDR 64bit 1GB */
+static struct mx6_ddr_sysinfo mem_dl = {
+       .dsize          = 2,
+       .cs1_mirror     = 0,
+       /* config for full 4GB range so that get_mem_size() works */
+       .cs_density     = 32,
+       .ncs            = 1,
+       .bi_on          = 1,
+       .rtt_nom        = 1,
+       .rtt_wr         = 1,
+       .ralat          = 5,
+       .walat          = 0,
+       .mif3_mode      = 3,
+       .rst_to_cke     = 0x23,
+       .sde_to_rst     = 0x10,
+};
+
+/* DDR 32bit 512MB */
+static struct mx6_ddr_sysinfo mem_s = {
+       .dsize          = 1,
+       .cs1_mirror     = 0,
+       /* config for full 4GB range so that get_mem_size() works */
+       .cs_density     = 32,
+       .ncs            = 1,
+       .bi_on          = 1,
+       .rtt_nom        = 1,
+       .rtt_wr         = 1,
+       .ralat          = 5,
+       .walat          = 0,
+       .mif3_mode      = 3,
+       .rst_to_cke     = 0x23,
+       .sde_to_rst     = 0x10,
+};
+
+static void ccgr_init(void)
+{
+       struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+       writel(0x00003F3F, &ccm->CCGR0);
+       writel(0x0030FC00, &ccm->CCGR1);
+       writel(0x000FC000, &ccm->CCGR2);
+       writel(0x3F300000, &ccm->CCGR3);
+       writel(0xFF00F300, &ccm->CCGR4);
+       writel(0x0F0000C3, &ccm->CCGR5);
+       writel(0x000003CC, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+       struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+       /* enable AXI cache for VDOA/VPU/IPU */
+       writel(0xF00000CF, &iomux->gpr[4]);
+       /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+       writel(0x007F007F, &iomux->gpr[6]);
+       writel(0x007F007F, &iomux->gpr[7]);
+}
+
+static void spl_dram_init(void)
+{
+       if (is_mx6solo()) {
+               mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+               mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
+       } else if (is_mx6dl()) {
+               mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+               mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
+       } else if (is_mx6dq()) {
+               mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
+               mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
+       }
+
+       udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+       ccgr_init();
+
+       /* setup AIPS and disable watchdog */
+       arch_cpu_init();
+
+       gpr_init();
+
+       /* iomux */
+       board_early_init_f();
+
+       /* setup GP timer */
+       timer_init();
+
+       /* UART clocks enabled and gd valid - init serial console */
+       preloader_console_init();
+
+       /* DDR initialization */
+       spl_dram_init();
+
+       /* Clear the BSS. */
+       memset(__bss_start, 0, __bss_end - __bss_start);
+
+       /* load/boot image from boot device */
+       board_init_r(NULL, 0);
+}
+#endif
diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig
new file mode 100644 (file)
index 0000000..ced6b10
--- /dev/null
@@ -0,0 +1,35 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6Q_ICORE=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb"
+CONFIG_SYS_PROMPT="icorem6qdl> "
+CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_LIBFDT=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h
new file mode 100644 (file)
index 0000000..0bd0f23
--- /dev/null
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * Configuration settings for the Engicam i.CoreM6 QDL Starter Kits.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __IMX6QLD_ICORE_CONFIG_H
+#define __IMX6QLD_ICORE_CONFIG_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          (16 * SZ_1M)
+
+/* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE                        SZ_128K
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment */
+#ifndef CONFIG_ENV_IS_NOWHERE
+/* Environment in MMC */
+# if defined(CONFIG_ENV_IS_IN_MMC)
+#  define CONFIG_ENV_OFFSET            0x100000
+# endif
+#endif
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       "script=boot.scr\0" \
+       "image=zImage\0" \
+       "console=ttymxc3\0" \
+       "fdt_high=0xffffffff\0" \
+       "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+       "fdt_addr=0x18000000\0" \
+       "boot_fdt=try\0" \
+       "mmcdev=0\0" \
+       "mmcpart=1\0" \
+       "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+       "mmcautodetect=yes\0" \
+       "mmcargs=setenv bootargs console=${console},${baudrate} " \
+               "root=${mmcroot}\0" \
+       "loadbootscript=" \
+               "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+       "bootscript=echo Running bootscript from mmc ...; " \
+               "source\0" \
+       "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+       "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+       "mmcboot=echo Booting from mmc ...; " \
+               "run mmcargs; " \
+               "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+                       "if run loadfdt; then " \
+                               "bootz ${loadaddr} - ${fdt_addr}; " \
+                       "else " \
+                               "if test ${boot_fdt} = try; then " \
+                                       "bootz; " \
+                               "else " \
+                                       "echo WARN: Cannot load the DT; " \
+                               "fi; " \
+                       "fi; " \
+               "else " \
+                       "bootz; " \
+               "fi\0"
+
+#define CONFIG_BOOTCOMMAND \
+          "mmc dev ${mmcdev};" \
+          "mmc dev ${mmcdev}; if mmc rescan; then " \
+                  "if run loadbootscript; then " \
+                          "run bootscript; " \
+                  "else " \
+                       "if run loadimage; then " \
+                               "run mmcboot; " \
+                       "fi; " \
+                  "fi; " \
+          "fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START       0x80000000
+#define CONFIG_SYS_MEMTEST_END         (CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+#define CONFIG_SYS_HZ                  1000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
+                                       GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_INIT_RAM_ADDR + \
+                                       CONFIG_SYS_INIT_SP_OFFSET)
+
+/* UART */
+#ifdef CONFIG_MXC_UART
+# define CONFIG_MXC_UART_BASE          UART4_BASE
+#endif
+
+/* MMC */
+#ifdef CONFIG_FSL_USDHC
+# define CONFIG_SYS_MMC_ENV_DEV                0
+# define CONFIG_SYS_FSL_USDHC_NUM      1
+# define CONFIG_SYS_FSL_ESDHC_ADDR     USDHC2_BASE_ADDR
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL
+# define CONFIG_SPL_MMC_SUPPORT
+# include "imx6_spl.h"
+#endif
+
+#endif /* __IMX6QLD_ICORE_CONFIG_H */