driver/ddr/fsl: Add support of overriding chip select write leveling
authorYork Sun <yorksun@freescale.com>
Fri, 5 Sep 2014 05:52:43 +0000 (13:52 +0800)
committerYork Sun <yorksun@freescale.com>
Mon, 8 Sep 2014 17:30:34 +0000 (10:30 -0700)
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.

Signed-off-by: York Sun <yorksun@freescale.com>
drivers/ddr/fsl/ctrl_regs.c
drivers/ddr/fsl/interactive.c
include/fsl_ddr_sdram.h

index 5e0ee77e46c6d28b4c8913789da52bda018b163e..d9cac2296a20afc431dcefa64bba109cd7e6a250 100644 (file)
@@ -2276,6 +2276,9 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
        if (ip_rev > 0x40400)
                unq_mrs_en = 1;
 
+       if (ip_rev > 0x40700)
+               ddr->debug[18] = popts->cswl_override;
+
        set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
        set_ddr_sdram_mode(ddr, popts, common_dimm,
                                cas_latency, additive_latency, unq_mrs_en);
index 7fb418744e0a32c55355f18c20fd6dbabd8501dc..6aa16b23ddc95f6df53077fd2c789141dee4eb19 100644 (file)
@@ -511,6 +511,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
                CTRL_OPTIONS(wrlvl_override),
                CTRL_OPTIONS(wrlvl_sample),
                CTRL_OPTIONS(wrlvl_start),
+               CTRL_OPTIONS(cswl_override),
                CTRL_OPTIONS(rcw_override),
                CTRL_OPTIONS(rcw_1),
                CTRL_OPTIONS(rcw_2),
@@ -801,6 +802,7 @@ static void print_memctl_options(const memctl_options_t *popts)
                CTRL_OPTIONS(wrlvl_override),
                CTRL_OPTIONS(wrlvl_sample),
                CTRL_OPTIONS(wrlvl_start),
+               CTRL_OPTIONS_HEX(cswl_override),
                CTRL_OPTIONS(rcw_override),
                CTRL_OPTIONS(rcw_1),
                CTRL_OPTIONS(rcw_2),
index e8a2db91cb7e115275ae13c70a498de4ee518239..987119b014ee513166fd4ba6cbaf47d405f2ef85 100644 (file)
@@ -281,6 +281,7 @@ typedef struct memctl_options_partial_s {
 #define DDR_DATA_BUS_WIDTH_64 0
 #define DDR_DATA_BUS_WIDTH_32 1
 #define DDR_DATA_BUS_WIDTH_16 2
+#define DDR_CSWL_CS0   0x04000001
 /*
  * Generalized parameters for memory controller configuration,
  * might be a little specific to the FSL memory controller
@@ -340,6 +341,7 @@ typedef struct memctl_options_s {
        unsigned int cpo_override;
        unsigned int write_data_delay;          /* DQS adjust */
 
+       unsigned int cswl_override;
        unsigned int wrlvl_override;
        unsigned int wrlvl_sample;              /* Write leveling */
        unsigned int wrlvl_start;