ColdFire: I2C fix for multiple platforms
authorTsiChung Liew <Tsi-Chung.Liew@freescale.com>
Mon, 18 Aug 2008 21:01:19 +0000 (03:01 +0600)
committerJohn Rigby <jrigby@freescale.com>
Thu, 28 Aug 2008 15:16:54 +0000 (09:16 -0600)
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
12 files changed:
cpu/mcf5227x/speed.c
cpu/mcf523x/cpu_init.c
cpu/mcf523x/speed.c
cpu/mcf52x2/cpu_init.c
cpu/mcf52x2/speed.c
cpu/mcf532x/speed.c
cpu/mcf5445x/speed.c
cpu/mcf547x_8x/speed.c
include/asm-m68k/fsl_i2c.h
include/configs/M5235EVB.h
include/configs/M5253DEMO.h
include/configs/M5275EVB.h

index 78c946f2583a68cdc196849228a4218c02a33c07..0baf9bcd997d29fee07788cf37b5bb966d736417 100644 (file)
@@ -116,5 +116,9 @@ int get_clocks(void)
                gd->bus_clk = gd->flb_clk;
        }
 
+#ifdef CONFIG_FSL_I2C
+       gd->i2c1_clk = gd->bus_clk;
+#endif
+
        return (0);
 }
index 55c9cd356d1525e3dd4077e6538376d568371993..8ab5b8ed8ba51ad7b8c9d915187a200538a3d64a 100644 (file)
@@ -110,8 +110,8 @@ void cpu_init_f(void)
 #endif
 
 #ifdef CONFIG_FSL_I2C
-       gpio->par_feci2c &= ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK);
-       gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA);
+       CFG_I2C_PINMUX_REG &= CFG_I2C_PINMUX_CLR;
+       CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET;
 #endif
 
        icache_enable();
index 247d3188bb200b143d0bd4dccc2043b2d0317f71..1bda2d482e6572695df033dbe33a206276fe9dd7 100644 (file)
@@ -45,5 +45,9 @@ int get_clocks(void)
        gd->bus_clk = CFG_CLK;
        gd->cpu_clk = (gd->bus_clk * 2);
 
+#ifdef CONFIG_FSL_I2C
+       gd->i2c1_clk = gd->bus_clk;
+#endif
+
        return (0);
 }
index 3cacb55f779f69fd05cd9f706ba96c8cfeffc9ec..68aefe9151b3032eaa851caf39875503a75d9e96 100644 (file)
@@ -80,6 +80,15 @@ void cpu_init_f(void)
        mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
        mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
 
+#ifdef CONFIG_FSL_I2C
+       CFG_I2C_PINMUX_REG = CFG_I2C_PINMUX_REG & CFG_I2C_PINMUX_CLR;
+       CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET;
+#ifdef CFG_I2C2_OFFSET
+       CFG_I2C2_PINMUX_REG &= CFG_I2C2_PINMUX_CLR;
+       CFG_I2C2_PINMUX_REG |= CFG_I2C2_PINMUX_SET;
+#endif
+#endif
+
        /* enable instruction cache now */
        icache_enable();
 }
@@ -322,7 +331,8 @@ void cpu_init_f(void)
 #endif                         /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
 
 #ifdef CONFIG_FSL_I2C
-       gpio_reg->par_feci2c = 0x000F;
+       CFG_I2C_PINMUX_REG &= CFG_I2C_PINMUX_CLR;
+       CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET;
 #endif
 
        /* enable instruction cache now */
index f6edd5b6fa81fa2bdaa6946bfc34567f91ecb1fc..4cb8f9300d9c8e97435e052cc7762781b9036deb 100644 (file)
@@ -82,5 +82,13 @@ int get_clocks (void)
 #else
        gd->bus_clk = gd->cpu_clk;
 #endif
+
+#ifdef CONFIG_FSL_I2C
+       gd->i2c1_clk = gd->bus_clk;
+#ifdef CFG_I2C2_OFFSET
+       gd->i2c2_clk = gd->bus_clk;
+#endif
+#endif
+
        return (0);
 }
index 001b9f42d64f3bf2e6f8fd03e30d0e914b1ca8f6..a11e425cab982d780dbc61390d68a1c9ce71e62f 100644 (file)
@@ -212,5 +212,10 @@ int get_clocks(void)
 {
        gd->bus_clk = clock_pll(CFG_CLK / 1000, 0) * 1000;
        gd->cpu_clk = (gd->bus_clk * 3);
+
+#ifdef CONFIG_FSL_I2C
+       gd->i2c1_clk = gd->bus_clk;
+#endif
+
        return (0);
 }
index f677f3ced0d007d9cb2deec0ad4407decbf0ede5..6711a1d7c89479b4e5030aea46ad417842c4084e 100644 (file)
@@ -209,5 +209,9 @@ int get_clocks(void)
 #endif
        }
 
+#ifdef CONFIG_FSL_I2C
+       gd->i2c1_clk = gd->bus_clk;
+#endif
+
        return (0);
 }
index 389e7c99f5252f29dcc0f2a2bc5541ab1e26cb48..28fe65729812e36c217c036250ff171fa99fe0ad 100644 (file)
@@ -39,5 +39,10 @@ int get_clocks(void)
 
        gd->bus_clk = CFG_CLK;
        gd->cpu_clk = (gd->bus_clk * 2);
+
+#ifdef CONFIG_FSL_I2C
+       gd->i2c1_clk = gd->bus_clk;
+#endif
+
        return (0);
 }
index 4f71341327bae7f5f9da6ce635295f3ea232adf6..2bc9bf434e1b1065f15e818f8c4a9f5545d837c6 100644 (file)
@@ -72,15 +72,6 @@ typedef struct fsl_i2c {
 #define I2C_DR         0xFF
 #define I2C_DR_SHIFT   0
 #define I2C_DR_RES     ~(I2C_DR)
-
-       u8 dfsrr;       /* I2C digital filter sampling rate register */
-       u8 res5[3];
-#define I2C_DFSRR      0x3F
-#define I2C_DFSRR_SHIFT        0
-#define I2C_DFSRR_RES  ~(I2C_DR)
-
-       /* Fill out the reserved block */
-       u8 res6[0xE8];
 } fsl_i2c_t;
 
 #endif /* _ASM_I2C_H_ */
index e8361321f171cc8c2da333f72cf75b9a9def5c4e..b32eabe9a37957c7940686735f0204ec7abd941c 100644 (file)
 
 /* I2C */
 #define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C                        /* I2C with hw support */
-#undef CONFIG_SOFT_I2C                 /* I2C bit-banged */
+#define CONFIG_HARD_I2C                /* I2C with hw support */
+#undef CONFIG_SOFT_I2C         /* I2C bit-banged */
 #define CFG_I2C_SPEED          80000
 #define CFG_I2C_SLAVE          0x7F
 #define CFG_I2C_OFFSET         0x00000300
 #define CFG_IMMR               CFG_MBAR
+#define CFG_I2C_PINMUX_REG     (gpio->par_qspi)
+#define CFG_I2C_PINMUX_CLR     ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
+#define CFG_I2C_PINMUX_SET     (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #define CONFIG_BOOTDELAY       1       /* autoboot after 5 seconds */
index f2c2317f50c0af797f559e4f126a43897eb424f3..9f78f6ebc88932b2248735496f226cc04d75298e 100644 (file)
 
 #define CONFIG_HOSTNAME                M5253DEMO
 
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C                /* I2C with hw support */
+#define CFG_I2C_SPEED          80000
+#define CFG_I2C_SLAVE          0x7F
+#define CFG_I2C_OFFSET         0x00000280
+#define CFG_IMMR               CFG_MBAR
+#define CFG_I2C_PINMUX_REG     (*(u32 *) (CFG_MBAR+0x19C))
+#define CFG_I2C_PINMUX_CLR     (0xFFFFE7FF)
+#define CFG_I2C_PINMUX_SET     (0)
+
 #define CFG_PROMPT             "=> "
 #define CFG_LONGHELP           /* undef to save memory */
 
index c1750b532aeea4b6c6d2671025ec6a9523200f0a..430af6bfa21a52d97c4a4098cbe9113b75bfff00 100644 (file)
 #define CFG_I2C_SLAVE          0x7F
 #define CFG_I2C_OFFSET         0x00000300
 #define CFG_IMMR               CFG_MBAR
+#define CFG_I2C_PINMUX_REG     (gpio_reg->par_feci2c)
+#define CFG_I2C_PINMUX_CLR     (0xFFF0)
+#define CFG_I2C_PINMUX_SET     (0x000F)
 
 #ifdef CONFIG_MCFFEC
 #define CONFIG_ETHADDR         00:06:3b:01:41:55