rockchip: Add common reset cause
authorJagan Teki <jagan@amarulasolutions.com>
Thu, 9 Jan 2020 08:52:18 +0000 (14:22 +0530)
committerKever Yang <kever.yang@rock-chips.com>
Thu, 30 Jan 2020 03:44:01 +0000 (11:44 +0800)
Add cpu reset cause in common cpu-info file.

This would help to print the reset cause for
various resets.

Right now it support rk3288, rk3399. rest of rockchip
platforms doesn't have reset cause support ye but this
code is more feasible to extend the same.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
arch/arm/include/asm/arch-rockchip/cru.h
arch/arm/include/asm/arch-rockchip/cru_rk3288.h
arch/arm/mach-rockchip/cpu-info.c
arch/arm/mach-rockchip/rk3288/rk3288.c

index 475d772fb648c4aefce6dbd4fb9e9d9e54c93d85..5cf2aec11a7cbe45f26f21b59198428f39feffc0 100644 (file)
 # include <asm/arch-rockchip/cru_rk3399.h>
 #endif
 
+/* CRU_GLB_RST_ST */
+enum {
+       GLB_POR_RST,
+       FST_GLB_RST_ST          = BIT(0),
+       SND_GLB_RST_ST          = BIT(1),
+       FST_GLB_TSADC_RST_ST    = BIT(2),
+       SND_GLB_TSADC_RST_ST    = BIT(3),
+       FST_GLB_WDT_RST_ST      = BIT(4),
+       SND_GLB_WDT_RST_ST      = BIT(5),
+       GLB_RST_ST_MASK         = GENMASK(5, 0),
+};
+
 #define MHz            1000000
 
 #endif /* _ROCKCHIP_CLOCK_H */
index 7aa6efe46c58618aa3df7c85ca183623ffdea986..412b73e55fa16ff1c16aa7b6fec29b1cbc704c91 100644 (file)
@@ -51,7 +51,7 @@ struct rockchip_cru {
        u32 cru_glb_cnt_th;
        u32 cru_glb_rst_con;
        u32 reserved3;
-       u32 cru_glb_rst_st;
+       u32 glb_rst_st;
        u32 reserved4;
        u32 cru_sdmmc_con[2];
        u32 cru_sdio0_con[2];
@@ -227,16 +227,4 @@ enum {
        CLKF_MASK               = 0x1fff << CLKF_SHIFT,
 };
 
-/* CRU_GLB_RST_ST */
-enum {
-       GLB_POR_RST,
-       FST_GLB_RST_ST          = BIT(0),
-       SND_GLB_RST_ST          = BIT(1),
-       FST_GLB_TSADC_RST_ST    = BIT(2),
-       SND_GLB_TSADC_RST_ST    = BIT(3),
-       FST_GLB_WDT_RST_ST      = BIT(4),
-       SND_GLB_WDT_RST_ST      = BIT(5),
-       GLB_RST_ST_MASK         = GENMASK(5, 0),
-};
-
 #endif
index 9bccbd4f68d930ae1e35abe2afad304108956b24..4b0e99299a06e10153ed008a1d47aa51cc239fe6 100644 (file)
@@ -5,10 +5,59 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <linux/err.h>
+
+static char *get_reset_cause(void)
+{
+       struct rockchip_cru *cru = rockchip_get_cru();
+       char *cause = NULL;
+
+       if (IS_ERR(cru))
+               return cause;
+
+       switch (cru->glb_rst_st) {
+       case GLB_POR_RST:
+               cause = "POR";
+               break;
+       case FST_GLB_RST_ST:
+       case SND_GLB_RST_ST:
+               cause = "RST";
+               break;
+       case FST_GLB_TSADC_RST_ST:
+       case SND_GLB_TSADC_RST_ST:
+               cause = "THERMAL";
+               break;
+       case FST_GLB_WDT_RST_ST:
+       case SND_GLB_WDT_RST_ST:
+               cause = "WDOG";
+               break;
+       default:
+               cause = "unknown reset";
+       }
+
+       /**
+        * reset_reason env is used by rk3288, due to special use case
+        * to figure it the boot behavior. so keep this as it is.
+        */
+       env_set("reset_reason", cause);
+
+       /*
+        * Clear glb_rst_st, so we can determine the last reset cause
+        * for following resets.
+        */
+       rk_clrreg(&cru->glb_rst_st, GLB_RST_ST_MASK);
+
+       return cause;
+}
 
 int print_cpuinfo(void)
 {
        printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC);
+       printf("Reset cause: %s\n", get_reset_cause());
 
        /* TODO print operating temparature and clock */
 
index 47ee5d440b3dc1aefb66626169fc80fb448f6e79..18ea7f35fbf869c8b67e342f48bcc2a1637ee636 100644 (file)
@@ -102,43 +102,6 @@ void board_debug_uart_init(void)
 }
 #endif
 
-static void rk3288_detect_reset_reason(void)
-{
-       struct rockchip_cru *cru = rockchip_get_cru();
-       const char *reason;
-
-       if (IS_ERR(cru))
-               return;
-
-       switch (cru->cru_glb_rst_st) {
-       case GLB_POR_RST:
-               reason = "POR";
-               break;
-       case FST_GLB_RST_ST:
-       case SND_GLB_RST_ST:
-               reason = "RST";
-               break;
-       case FST_GLB_TSADC_RST_ST:
-       case SND_GLB_TSADC_RST_ST:
-               reason = "THERMAL";
-               break;
-       case FST_GLB_WDT_RST_ST:
-       case SND_GLB_WDT_RST_ST:
-               reason = "WDOG";
-               break;
-       default:
-               reason = "unknown reset";
-       }
-
-       env_set("reset_reason", reason);
-
-       /*
-        * Clear cru_glb_rst_st, so we can determine the last reset cause
-        * for following resets.
-        */
-       rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
-}
-
 __weak int rk3288_board_late_init(void)
 {
        return 0;
@@ -146,8 +109,6 @@ __weak int rk3288_board_late_init(void)
 
 int rk_board_late_init(void)
 {
-       rk3288_detect_reset_reason();
-
        return rk3288_board_late_init();
 }