ARM: keystone2: Add support for getting external clock dynamically

One some keystone2 platforms like K2G ICE, there is an option
to switch between 24MHz or 25MHz as sysclk. But the existing
driver assumes it is always 24MHz. Add support for getting
all reference clocks dynamically by reading boot pins.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
index 68f898036ff8b98857b96d6b0ca595161548463b..645bd9629e850fa7501f6ab94f1858e4135d8ac7 100644 (file)
--- a/arch/arm/mach-keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
@@ -284,7 +284,7 @@ static unsigned long pll_freq_get(int pll)
        u32 tmp, reg;
 
        if (pll == MAIN_PLL) {
-               ret = external_clk[sys_clk];
+               ret = get_external_clk(sys_clk);
                if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN_MASK) {
                        /* PLL mode */
                        tmp = __raw_readl(KS2_MAINPLLCTL0);
@@ -302,23 +302,23 @@ static unsigned long pll_freq_get(int pll)
        } else {
                switch (pll) {
                case PASS_PLL:
-                       ret = external_clk[pa_clk];
+                       ret = get_external_clk(pa_clk);
                        reg = KS2_PASSPLLCTL0;
                        break;
                case TETRIS_PLL:
-                       ret = external_clk[tetris_clk];
+                       ret = get_external_clk(tetris_clk);
                        reg = KS2_ARMPLLCTL0;
                        break;
                case DDR3A_PLL:
-                       ret = external_clk[ddr3a_clk];
+                       ret = get_external_clk(ddr3a_clk);
                        reg = KS2_DDR3APLLCTL0;
                        break;
                case DDR3B_PLL:
-                       ret = external_clk[ddr3b_clk];
+                       ret = get_external_clk(ddr3b_clk);
                        reg = KS2_DDR3BPLLCTL0;
                        break;
                case UART_PLL:
-                       ret = external_clk[uart_clk];
+                       ret = get_external_clk(uart_clk);
                        reg = KS2_UARTPLLCTL0;
                        break;
                default:

diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
index 0d8a9444ded9f6cfa5e6d204930893d1a99b0151..006d0744d1c3ccbc1fafbfcd86ac90101e6dcdc1 100644 (file)
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -117,7 +117,6 @@ struct pll_init_data {
        int pll_od;             /* PLL output divider */
 };
 
-extern unsigned int external_clk[ext_clk_count];
 extern const struct keystone_pll_regs keystone_pll_regs[];
 extern s16 divn_val[];
 extern int speeds[];
@@ -129,6 +128,7 @@ unsigned long ks_clk_get_rate(unsigned int clk);
 int get_max_dev_speed(int *spds);
 int get_max_arm_speed(int *spds);
 void pll_pa_clk_sel(void);
+unsigned int get_external_clk(u32 clk);
 
 #endif
 #endif

diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index cbb3077bc36ca4ff4d5abdc75e5a7aabe5649606..64f0c9cd5b5c5b4300967205372762a38cc177a0 100644 (file)
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -14,12 +14,30 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-unsigned int external_clk[ext_clk_count] = {
-       [sys_clk]       = 100000000,
-       [alt_core_clk]  = 100000000,
-       [pa_clk]        = 100000000,
-       [ddr3a_clk]     = 100000000,
-};
+unsigned int get_external_clk(u32 clk)
+{
+       unsigned int clk_freq;
+
+       switch (clk) {
+       case sys_clk:
+               clk_freq = 100000000;
+               break;
+       case alt_core_clk:
+               clk_freq = 100000000;
+               break;
+       case pa_clk:
+               clk_freq = 100000000;
+               break;
+       case ddr3a_clk:
+               clk_freq = 100000000;
+               break;
+       default:
+               clk_freq = 0;
+               break;
+       }
+
+       return clk_freq;
+}
 
 static struct pll_init_data core_pll_config[NUM_SPDS] = {
        [SPD800]        = CORE_PLL_800,

diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index 20933426b1d62f02cb89e72e74a6a16913bca668..6e03f6bcd027296d6fcbb02c54df1df18c644555 100644 (file)
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -14,8 +14,6 @@
 #include "mux-k2g.h"
 #include "../common/board_detect.h"
 
-#define SYS_CLK                24000000
-
 const unsigned int sysclk_array[MAX_SYSCLK] = {
        19200000,
        24000000,
@@ -23,13 +21,34 @@ const unsigned int sysclk_array[MAX_SYSCLK] = {
        26000000,
 };
 
-unsigned int external_clk[ext_clk_count] = {
-       [sys_clk]       =       SYS_CLK,
-       [pa_clk]        =       SYS_CLK,
-       [tetris_clk]    =       SYS_CLK,
-       [ddr3a_clk]     =       SYS_CLK,
-       [uart_clk]      =       SYS_CLK,
-};
+unsigned int get_external_clk(u32 clk)
+{
+       unsigned int clk_freq;
+       u8 sysclk_index = get_sysclk_index();
+
+       switch (clk) {
+       case sys_clk:
+               clk_freq = sysclk_array[sysclk_index];
+               break;
+       case pa_clk:
+               clk_freq = sysclk_array[sysclk_index];
+               break;
+       case tetris_clk:
+               clk_freq = sysclk_array[sysclk_index];
+               break;
+       case ddr3a_clk:
+               clk_freq = sysclk_array[sysclk_index];
+               break;
+       case uart_clk:
+               clk_freq = sysclk_array[sysclk_index];
+               break;
+       default:
+               clk_freq = 0;
+               break;
+       }
+
+       return clk_freq;
+}
 
 static int arm_speeds[DEVSPEED_NUMSPDS] = {
        SPD400,

diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
index e217beaed5e4494fd900d8a0acbcb259926b38da..b35f24d7b5812510caddb448dd8966c6d8881569 100644 (file)
--- a/board/ti/ks2_evm/board_k2hk.c
+++ b/board/ti/ks2_evm/board_k2hk.c
@@ -23,6 +23,37 @@ unsigned int external_clk[ext_clk_count] = {
        [ddr3b_clk]     =       100000000,
 };
 
+unsigned int get_external_clk(u32 clk)
+{
+       unsigned int clk_freq;
+
+       switch (clk) {
+       case sys_clk:
+               clk_freq = 122880000;
+               break;
+       case alt_core_clk:
+               clk_freq = 125000000;
+               break;
+       case pa_clk:
+               clk_freq = 122880000;
+               break;
+       case tetris_clk:
+               clk_freq = 125000000;
+               break;
+       case ddr3a_clk:
+               clk_freq = 100000000;
+               break;
+       case ddr3b_clk:
+               clk_freq = 100000000;
+               break;
+       default:
+               clk_freq = 0;
+               break;
+       }
+
+       return clk_freq;
+}
+
 static struct pll_init_data core_pll_config[NUM_SPDS] = {
        [SPD800]        = CORE_PLL_799,
        [SPD1000]       = CORE_PLL_999,

diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
index 2a2e0057e24efd2fd4832f5e07c025de102c4a09..f3eea4200cbd0def1fbcfe48097fda507de00251 100644 (file)
--- a/board/ti/ks2_evm/board_k2l.c
+++ b/board/ti/ks2_evm/board_k2l.c
@@ -14,13 +14,33 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-unsigned int external_clk[ext_clk_count] = {
-       [sys_clk]       = 122880000,
-       [alt_core_clk]  = 100000000,
-       [pa_clk]        = 122880000,
-       [tetris_clk]    = 122880000,
-       [ddr3a_clk]     = 100000000,
-};
+unsigned int get_external_clk(u32 clk)
+{
+       unsigned int clk_freq;
+
+       switch (clk) {
+       case sys_clk:
+               clk_freq = 122880000;
+               break;
+       case alt_core_clk:
+               clk_freq = 100000000;
+               break;
+       case pa_clk:
+               clk_freq = 122880000;
+               break;
+       case tetris_clk:
+               clk_freq = 122880000;
+               break;
+       case ddr3a_clk:
+               clk_freq = 100000000;
+               break;
+       default:
+               clk_freq = 0;
+               break;
+       }
+
+       return clk_freq;
+}
 
 static struct pll_init_data core_pll_config[NUM_SPDS] = {
        [SPD800]        = CORE_PLL_799,

diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 5d2a7ab509e320e9f0e6495dd3314abd3be27975..868464cd320ad4cf4862a0d9281f8bf0323459ba 100644 (file)
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -318,7 +318,7 @@
 #ifndef CONFIG_SOC_K2G
 #define CONFIG_SYS_HZ_CLOCK            ks_clk_get_rate(KS2_CLK1_6)
 #else
-#define CONFIG_SYS_HZ_CLOCK            external_clk[sys_clk]
+#define CONFIG_SYS_HZ_CLOCK            get_external_clk(sys_clk)
 #endif
 
 #endif /* __CONFIG_KS2_EVM_H */