u8 value;
/* read Chip variant */
- if (device_is_compatible(dev, "rockchip,rk817")) {
+ if (device_is_compatible(dev, "rockchip,rk817") ||
+ device_is_compatible(dev, "rockchip,rk809")) {
id_msb = RK817_ID_MSB;
id_lsb = RK817_ID_LSB;
} else {
on_source = RK8XX_ON_SOURCE;
off_source = RK8XX_OFF_SOURCE;
break;
+ case RK809_ID:
case RK817_ID:
on_source = RK817_ON_SOURCE;
off_source = RK817_OFF_SOURCE;
static const struct udevice_id rk8xx_ids[] = {
{ .compatible = "rockchip,rk805" },
{ .compatible = "rockchip,rk808" },
+ { .compatible = "rockchip,rk809" },
{ .compatible = "rockchip,rk816" },
{ .compatible = "rockchip,rk817" },
{ .compatible = "rockchip,rk818" },
#define RK808_BUCK4_VSEL_MASK 0xf
#define RK808_LDO_VSEL_MASK 0x1f
+/* RK809 BUCK5 */
+#define RK809_BUCK5_CONFIG(n) (0xde + (n) * 1)
+#define RK809_BUCK5_VSEL_MASK 0x07
+
/* RK817 BUCK */
#define RK817_BUCK_ON_VSEL(n) (0xbb + 3 * ((n) - 1))
#define RK817_BUCK_SLP_VSEL(n) (0xbc + 3 * ((n) - 1))
#define RK805_RAMP_RATE_6MV_PER_US (1 << RK805_RAMP_RATE_OFFSET)
#define RK805_RAMP_RATE_12_5MV_PER_US (2 << RK805_RAMP_RATE_OFFSET)
#define RK805_RAMP_RATE_25MV_PER_US (3 << RK805_RAMP_RATE_OFFSET)
+
#define RK808_RAMP_RATE_OFFSET 3
#define RK808_RAMP_RATE_MASK (3 << RK808_RAMP_RATE_OFFSET)
#define RK808_RAMP_RATE_2MV_PER_US (0 << RK808_RAMP_RATE_OFFSET)
{ 800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, },
};
+static const struct rk8xx_reg_info rk809_buck5[] = {
+ /* buck 5 */
+ { 1500000, 0, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x00, },
+ { 1800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x01, },
+ { 2800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x04, },
+ { 3300000, 300000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x06, },
+};
+
static const struct rk8xx_reg_info rk817_buck[] = {
/* buck 1 */
{ 500000, 12500, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x00, },
return &rk816_buck[num + 4];
}
+ case RK809_ID:
case RK817_ID:
switch (num) {
case 0 ... 2:
return &rk817_buck[num * 3 + 1];
else
return &rk817_buck[num * 3 + 2];
+ /* BUCK5 for RK809 */
+ default:
+ if (uvolt < 1800000)
+ return &rk809_buck5[0];
+ else if (uvolt < 2800000)
+ return &rk809_buck5[1];
+ else if (uvolt < 3300000)
+ return &rk809_buck5[2];
+ else
+ return &rk809_buck5[3];
}
case RK818_ID:
return &rk818_buck[num];
ret = pmic_clrsetbits(pmic, REG_DCDC_EN, mask,
enable ? mask : 0);
break;
+ case RK809_ID:
case RK817_ID:
if (buck < 4) {
if (enable)
else
value = ((0 << buck) | (1 << (buck + 4)));
ret = pmic_reg_write(pmic, RK817_POWER_EN(0), value);
+ /* BUCK5 for RK809 */
+ } else {
+ if (enable)
+ value = ((1 << 1) | (1 << 5));
+ else
+ value = ((0 << 1) | (1 << 5));
+ ret = pmic_reg_write(pmic, RK817_POWER_EN(3), value);
}
break;
default:
if (ret < 0)
return ret;
break;
+ case RK809_ID:
case RK817_ID:
if (buck < 4) {
mask = 1 << buck;
ret = pmic_reg_read(pmic, RK817_POWER_EN(0));
+ /* BUCK5 for RK809 */
+ } else {
+ mask = 1 << 1;
+ ret = pmic_reg_read(pmic, RK817_POWER_EN(3));
}
break;
}
ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF1, mask,
enable ? 0 : mask);
break;
+ case RK809_ID:
case RK817_ID:
if (buck < 4)
mask = 1 << buck;
+ else
+ mask = 1 << 5; /* BUCK5 for RK809 */
ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask,
enable ? mask : 0);
break;
return val;
ret = val & mask ? 0 : 1;
break;
+ case RK809_ID:
case RK817_ID:
if (buck < 4)
mask = 1 << buck;
+ else
+ mask = 1 << 5; /* BUCK5 for RK809 */
val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0));
if (val < 0)
case RK805_ID:
case RK816_ID:
return &rk816_ldo[num];
+ case RK809_ID:
case RK817_ID:
if (uvolt < 3400000)
return &rk817_ldo[num * 2 + 0];
if (ret < 0)
return ret;
break;
+ case RK809_ID:
case RK817_ID:
if (ldo < 4) {
mask = 1 << ldo;
ret = pmic_clrsetbits(pmic, REG_LDO_EN, mask,
enable ? mask : 0);
break;
+ case RK809_ID:
case RK817_ID:
if (ldo < 4) {
en_reg = RK817_POWER_EN(1);
ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF2, mask,
enable ? 0 : mask);
break;
+ case RK809_ID:
case RK817_ID:
if (ldo == 8) {
mask = 1 << 4; /* LDO9 */
return val;
ret = val & mask ? 0 : 1;
break;
+ case RK809_ID:
case RK817_ID:
if (ldo == 8) {
mask = 1 << 4; /* LDO9 */
ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask,
enable ? mask : 0);
break;
+ case RK809_ID:
+ mask = (1 << (sw + 2)) | (1 << (sw + 6));
+ ret = pmic_clrsetbits(dev->parent, RK817_POWER_EN(3), mask,
+ enable ? mask : 0);
+ break;
case RK818_ID:
mask = 1 << 6;
ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask,
mask = 1 << (sw + 5);
ret = pmic_reg_read(dev->parent, REG_DCDC_EN);
break;
+ case RK809_ID:
+ mask = 1 << (sw + 2);
+ ret = pmic_reg_read(dev->parent, RK817_POWER_EN(3));
+ break;
case RK818_ID:
mask = 1 << 6;
ret = pmic_reg_read(dev->parent, REG_DCDC_EN);
ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask,
enable ? 0 : mask);
break;
+ case RK809_ID:
+ mask = 1 << (sw + 6);
+ ret = pmic_clrsetbits(dev->parent, RK817_POWER_SLP_EN(0), mask,
+ enable ? mask : 0);
+ break;
case RK818_ID:
mask = 1 << 6;
ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask,
return val;
ret = val & mask ? 0 : 1;
break;
+ case RK809_ID:
+ mask = 1 << (sw + 6);
+ val = pmic_reg_read(dev->parent, RK817_POWER_SLP_EN(0));
+ if (val < 0)
+ return val;
+ ret = val & mask ? 1 : 0;
+ break;
case RK818_ID:
mask = 1 << 6;
val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1);