ARM: dts: UniPhier: sync device trees with the Linux kernel

This makes code diff much easier.

Device trees describe hardware attributes, which are independent
of software architecture.  It generally makes sense to synchronize
them beyond software projects.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index c2008383c1b499c2753a2b7d207be2347c14ec12..c3553953492379a0309dcd0848111bc9c47291f8 100644 (file)
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -1,9 +1,7 @@
 /*
  * Device Tree Source for UniPhier PH1-LD4 SoC
  *
- * Copyright (C) 2014-2015 Panasonic Corporation
- * Copyright (C) 2015      Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -24,11 +22,26 @@
                };
        };
 
+       clocks {
+               arm_timer_clk: arm_timer_clk {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <50000000>;
+               };
+       };
+
        soc {
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
                ranges;
+               interrupt-parent = <&intc>;
+
+               extbus: extbus {
+                       compatible = "simple-bus";
+                       #address-cells = <2>;
+                       #size-cells = <1>;
+               };
 
                uart0: serial@54006800 {
                        compatible = "socionext,uniphier-uart";
@@ -94,6 +107,12 @@
                        status = "disabled";
                };
 
+               system-bus-controller-misc@59800000 {
+                       compatible = "socionext,uniphier-system-bus-controller-misc",
+                                    "syscon";
+                       reg = <0x59800000 0x2000>;
+               };
+
                usb0: usb@5a800100 {
                        compatible = "socionext,uniphier-ehci", "generic-ehci";
                        status = "disabled";
@@ -112,6 +131,28 @@
                        reg = <0x5a820100 0x100>;
                };
 
+               timer@60000200 {
+                       compatible = "arm,cortex-a9-global-timer";
+                       reg = <0x60000200 0x20>;
+                       interrupts = <1 11 0x104>;
+                       clocks = <&arm_timer_clk>;
+               };
+
+               timer@60000600 {
+                       compatible = "arm,cortex-a9-twd-timer";
+                       reg = <0x60000600 0x20>;
+                       interrupts = <1 13 0x104>;
+                       clocks = <&arm_timer_clk>;
+               };
+
+               intc: interrupt-controller@60001000 {
+                       compatible = "arm,cortex-a9-gic";
+                       #interrupt-cells = <3>;
+                       interrupt-controller;
+                       reg = <0x60001000 0x1000>,
+                             <0x60000100 0x100>;
+               };
+
                nand: nand@68000000 {
                        compatible = "denali,denali-nand-dt";
                        reg = <0x68000000 0x20>, <0x68100000 0x1000>;

diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index 8195266db3c7ab2f88b459af41d331ae40fad105..5c82df7ccda50217b677ea7c9e9c3067b4545a03 100644 (file)
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -1,9 +1,7 @@
 /*
  * Device Tree Source for UniPhier PH1-Pro4 SoC
  *
- * Copyright (C) 2014-2015 Panasonic Corporation
- * Copyright (C) 2015      Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -16,6 +14,7 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
+               enable-method = "socionext,uniphier-smp";
 
                cpu@0 {
                        device_type = "cpu";
@@ -30,11 +29,26 @@
                };
        };
 
+       clocks {
+               arm_timer_clk: arm_timer_clk {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <50000000>;
+               };
+       };
+
        soc {
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
                ranges;
+               interrupt-parent = <&intc>;
+
+               extbus: extbus {
+                       compatible = "simple-bus";
+                       #address-cells = <2>;
+                       #size-cells = <1>;
+               };
 
                uart0: serial@54006800 {
                        compatible = "socionext,uniphier-uart";
@@ -120,6 +134,12 @@
                        status = "ok";
                };
 
+               system-bus-controller-misc@59800000 {
+                       compatible = "socionext,uniphier-system-bus-controller-misc",
+                                    "syscon";
+                       reg = <0x59800000 0x2000>;
+               };
+
                usb2: usb@5a800100 {
                        compatible = "socionext,uniphier-ehci", "generic-ehci";
                        status = "disabled";
@@ -144,6 +164,28 @@
                        reg = <0x65c00000 0x100>;
                };
 
+               timer@60000200 {
+                       compatible = "arm,cortex-a9-global-timer";
+                       reg = <0x60000200 0x20>;
+                       interrupts = <1 11 0x304>;
+                       clocks = <&arm_timer_clk>;
+               };
+
+               timer@60000600 {
+                       compatible = "arm,cortex-a9-twd-timer";
+                       reg = <0x60000600 0x20>;
+                       interrupts = <1 13 0x304>;
+                       clocks = <&arm_timer_clk>;
+               };
+
+               intc: interrupt-controller@60001000 {
+                       compatible = "arm,cortex-a9-gic";
+                       #interrupt-cells = <3>;
+                       interrupt-controller;
+                       reg = <0x60001000 0x1000>,
+                             <0x60000100 0x100>;
+               };
+
                nand: nand@68000000 {
                        compatible = "denali,denali-nand-dt";
                        reg = <0x68000000 0x20>, <0x68100000 0x1000>;

diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi
index 44b19897b3bd87817e267d9e075a372dfbe73a58..1f93bb95aafc8ef9a7641d82e24435819bde57ee 100644 (file)
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -1,9 +1,7 @@
 /*
  * Device Tree Source for UniPhier PH1-sLD3 SoC
  *
- * Copyright (C) 2014-2015 Panasonic Corporation
- * Copyright (C) 2015      Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -16,6 +14,7 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
+               enable-method = "socionext,uniphier-smp";
 
                cpu@0 {
                        device_type = "cpu";
@@ -30,11 +29,48 @@
                };
        };
 
+       clocks {
+               arm_timer_clk: arm_timer_clk {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <50000000>;
+               };
+       };
+
        soc {
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
                ranges;
+               interrupt-parent = <&intc>;
+
+               extbus: extbus {
+                       compatible = "simple-bus";
+                       #address-cells = <2>;
+                       #size-cells = <1>;
+               };
+
+               timer@20000200 {
+                       compatible = "arm,cortex-a9-global-timer";
+                       reg = <0x20000200 0x20>;
+                       interrupts = <1 11 0x304>;
+                       clocks = <&arm_timer_clk>;
+               };
+
+               timer@20000600 {
+                       compatible = "arm,cortex-a9-twd-timer";
+                       reg = <0x20000600 0x20>;
+                       interrupts = <1 13 0x304>;
+                       clocks = <&arm_timer_clk>;
+               };
+
+               intc: interrupt-controller@20001000 {
+                       compatible = "arm,cortex-a9-gic";
+                       #interrupt-cells = <3>;
+                       interrupt-controller;
+                       reg = <0x20001000 0x1000>,
+                             <0x20000100 0x100>;
+               };
 
                uart0: serial@54006800 {
                        compatible = "socionext,uniphier-uart";
@@ -93,6 +129,12 @@
                        status = "disabled";
                };
 
+               system-bus-controller-misc@59800000 {
+                       compatible = "socionext,uniphier-system-bus-controller-misc",
+                                    "syscon";
+                       reg = <0x59800000 0x2000>;
+               };
+
                usb0: usb@5a800100 {
                        compatible = "socionext,uniphier-ehci", "generic-ehci";
                        status = "disabled";

diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index d9f61c2231968621bc0b407c91b47ca3ed5bcdd7..4f291f7987d0ea607f725f374cbc9aee4885ef2e 100644 (file)
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -1,9 +1,7 @@
 /*
  * Device Tree Source for UniPhier PH1-sLD8 SoC
  *
- * Copyright (C) 2014-2015 Panasonic Corporation
- * Copyright (C) 2015      Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -24,11 +22,26 @@
                };
        };
 
+       clocks {
+               arm_timer_clk: arm_timer_clk {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <50000000>;
+               };
+       };
+
        soc {
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
                ranges;
+               interrupt-parent = <&intc>;
+
+               extbus: extbus {
+                       compatible = "simple-bus";
+                       #address-cells = <2>;
+                       #size-cells = <1>;
+               };
 
                uart0: serial@54006800 {
                        compatible = "socionext,uniphier-uart";
@@ -94,6 +107,12 @@
                        status = "disabled";
                };
 
+               system-bus-controller-misc@59800000 {
+                       compatible = "socionext,uniphier-system-bus-controller-misc",
+                                    "syscon";
+                       reg = <0x59800000 0x2000>;
+               };
+
                usb0: usb@5a800100 {
                        compatible = "socionext,uniphier-ehci", "generic-ehci";
                        status = "disabled";
@@ -112,6 +131,28 @@
                        reg = <0x5a820100 0x100>;
                };
 
+               timer@60000200 {
+                       compatible = "arm,cortex-a9-global-timer";
+                       reg = <0x60000200 0x20>;
+                       interrupts = <1 11 0x104>;
+                       clocks = <&arm_timer_clk>;
+               };
+
+               timer@60000600 {
+                       compatible = "arm,cortex-a9-twd-timer";
+                       reg = <0x60000600 0x20>;
+                       interrupts = <1 13 0x104>;
+                       clocks = <&arm_timer_clk>;
+               };
+
+               intc: interrupt-controller@60001000 {
+                       compatible = "arm,cortex-a9-gic";
+                       #interrupt-cells = <3>;
+                       interrupt-controller;
+                       reg = <0x60001000 0x1000>,
+                             <0x60000100 0x100>;
+               };
+
                nand: nand@68000000 {
                        compatible = "denali,denali-nand-dt";
                        reg = <0x68000000 0x20>, <0x68100000 0x1000>;