armv8: fsl: remove sata support

Remove the old implementation in order to enable DM for sata.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index bfd663942aa23140741ef8ceadc795bdd4045274..8028d5228f49711dfe2977b660c644fa145593a6 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -6,8 +6,6 @@
 #include <common.h>
 #include <fsl_immap.h>
 #include <fsl_ifc.h>
-#include <ahci.h>
-#include <scsi.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/soc.h>
 #include <asm/io.h>
@@ -330,36 +328,6 @@ void fsl_lsch3_early_init_f(void)
 #endif
 }
 
-#ifdef CONFIG_SCSI_AHCI_PLAT
-int sata_init(void)
-{
-       struct ccsr_ahci __iomem *ccsr_ahci;
-
-#ifdef CONFIG_SYS_SATA2
-       ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
-       out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
-       out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
-       out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
-       out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
-       out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
-#endif
-
-#ifdef CONFIG_SYS_SATA1
-       ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
-       out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
-       out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
-       out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
-       out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
-       out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
-
-       ahci_init((void __iomem *)CONFIG_SYS_SATA1);
-       scsi_scan(false);
-#endif
-
-       return 0;
-}
-#endif
-
 /* Get VDD in the unit mV from voltage ID */
 int get_core_volt_from_fuse(void)
 {
@@ -400,25 +368,6 @@ int get_core_volt_from_fuse(void)
 }
 
 #elif defined(CONFIG_FSL_LSCH2)
-#ifdef CONFIG_SCSI_AHCI_PLAT
-int sata_init(void)
-{
-       struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
-
-       /* Disable SATA ECC */
-       out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
-       out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
-       out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
-       out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
-       out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
-       out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
-
-       ahci_init((void __iomem *)CONFIG_SYS_SATA);
-       scsi_scan(false);
-
-       return 0;
-}
-#endif
 
 static void erratum_a009929(void)
 {
@@ -719,9 +668,6 @@ int qspi_ahb_init(void)
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
-#ifdef CONFIG_SCSI_AHCI_PLAT
-       sata_init();
-#endif
 #ifdef CONFIG_CHAIN_OF_TRUST
        fsl_setenv_chain_of_trust();
 #endif

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 9a219a6a1d55ad5ff30f51e0ede51a7dc6a00161..6e3a420f48668e9d4939d028e4f87d9d10a85e1d 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -85,39 +85,7 @@ struct cpu_type {
 #define SVR_DEV(svr)           ((svr) >> 8)
 #define IS_SVR_DEV(svr, dev)   (((svr) >> 16) == (dev))
 
-/* ahci port register default value */
-#define AHCI_PORT_PHY_1_CFG    0xa003fffe
-#define AHCI_PORT_PHY2_CFG     0x28184d1f
-#define AHCI_PORT_PHY3_CFG     0x0e081509
-#define AHCI_PORT_TRANS_CFG    0x08000029
-#define AHCI_PORT_AXICC_CFG    0x3fffffff
-
 #ifndef __ASSEMBLY__
-/* AHCI (sata) register map */
-struct ccsr_ahci {
-       u32 res1[0xa4/4];       /* 0x0 - 0xa4 */
-       u32 pcfg;       /* port config */
-       u32 ppcfg;      /* port phy1 config */
-       u32 pp2c;       /* port phy2 config */
-       u32 pp3c;       /* port phy3 config */
-       u32 pp4c;       /* port phy4 config */
-       u32 pp5c;       /* port phy5 config */
-       u32 axicc;      /* AXI cache control */
-       u32 paxic;      /* port AXI config */
-       u32 axipc;      /* AXI PROT control */
-       u32 ptc;        /* port Trans Config */
-       u32 pts;        /* port Trans Status */
-       u32 plc;        /* port link config */
-       u32 plc1;       /* port link config1 */
-       u32 plc2;       /* port link config2 */
-       u32 pls;        /* port link status */
-       u32 pls1;       /* port link status1 */
-       u32 pcmdc;      /* port CMD config */
-       u32 ppcs;       /* port phy control status */
-       u32 pberr;      /* port 0/1 BIST error */
-       u32 cmds;       /* port 0/1 CMD status error */
-};
-
 #ifdef CONFIG_FSL_LSCH3
 void fsl_lsch3_early_init_f(void);
 int get_core_volt_from_fuse(void);