board: ge: bx50v3: apply the proper register setting to fix the voltage peak issue

Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register
to avoid the voltage peak issue while we do the IEEE PHY comformance test

Signed-off-by: Ken Lin <yungching0725@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Ian Ray <ian.ray@ge.com>

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 80b4ba1b8bf113a9cca1a76c76957d270fde0117..0acf655c0e5b86686ea1d32471ba1ab1c4122f2a 100644 (file)
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -307,7 +307,8 @@ static int mx6_rgmii_rework(struct phy_device *phydev)
        /* set debug port address: SerDes Test and System Mode Control */
        phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
        /* enable rgmii tx clock delay */
-       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+       /* set the reserved bits to avoid board specific voltage peak issue*/
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 
        return 0;
 }