device memory. Assure this size does not extend past expected storage
space.
+config FIT_ENABLE_RSASSA_PSS_SUPPORT
+ bool "Support rsassa-pss signature scheme of FIT image contents"
+ depends on FIT_SIGNATURE
+ default n
+ help
+ Enable this to support the pss padding algorithm as described
+ in the rfc8017 (https://tools.ietf.org/html/rfc8017).
+
config FIT_VERBOSE
bool "Show verbose messages when FIT images fail"
help
* access: "lr"/"sr".
*/
+/*
+ * Typically 8 least significant bits of Build Configuration Register (BCR)
+ * describe version of the HW block in question. Moreover if decoded version
+ * is 0 this means given HW block is absent - this is especially useful because
+ * we may safely read BRC regardless HW block existence while an attempt to
+ * access any other AUX regs associated with this HW block lead to imediate
+ * "instruction error" exception.
+ *
+ * I.e. before using any cofigurable HW block it's required to make sure it
+ * exists at all, and for that we introduce a special macro below.
+ */
+#define ARC_BCR_VERSION_MASK GENMASK(7, 0)
+#define ARC_FEATURE_EXISTS(bcr) !!(__builtin_arc_lr(bcr) & ARC_BCR_VERSION_MASK)
+
#define ARC_AUX_IDENTITY 0x04
#define ARC_AUX_STATUS32 0x0a
#define ARC_BCR_CLUSTER 0xcf
/* MMU Management regs */
-#define ARC_AUX_MMU_BCR 0x06f
+#define ARC_AUX_MMU_BCR 0x6f
/* IO coherency related auxiliary registers */
#define ARC_AUX_IO_COH_ENABLE 0x500
#define ARC_AUX_IO_COH_AP0_BASE 0x508
#define ARC_AUX_IO_COH_AP0_SIZE 0x509
+/* XY-memory related */
+#define ARC_AUX_XY_BUILD 0x79
+
+/* DSP-extensions related auxiliary registers */
+#define ARC_AUX_DSP_BUILD 0x7A
+
+/* ARC Subsystems related auxiliary registers */
+#define ARC_AUX_SUBSYS_BUILD 0xF0
+
#ifndef __ASSEMBLY__
/* Accessors for auxiliary registers */
#define read_aux_reg(reg) __builtin_arc_lr(reg)
*/
#include <common.h>
+#include <malloc.h>
#include <asm/arcregs.h>
#include <asm/cache.h>
}
#ifdef CONFIG_DISPLAY_CPUINFO
-const char *decode_identity(void)
+const char *arc_700_version(int arcver, char *name, int name_len)
{
- int arcver = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
+ const char *arc_ver;
+
+ switch (arcver) {
+ case 0x32:
+ arc_ver = "v4.4-4.5";
+ break;
+ case 0x33:
+ arc_ver = "v4.6-v4.9";
+ break;
+ case 0x34:
+ arc_ver = "v4.10";
+ break;
+ case 0x35:
+ arc_ver = "v4.11";
+ break;
+ default:
+ arc_ver = "unknown version";
+ }
+
+ snprintf(name, name_len, "ARC 700 %s", arc_ver);
+
+ return name;
+}
+
+struct em_template_t {
+ const bool cache;
+ const bool dsp;
+ const bool xymem;
+ const char name[8];
+};
+
+static const struct em_template_t em_versions[] = {
+ {false, false, false, "EM4"},
+ {true, false, false, "EM6"},
+ {false, true, false, "EM5D"},
+ {true, true, false, "EM7D"},
+ {false, true, true, "EM9D"},
+ {true, true, true, "EM11D"},
+};
+
+const char *arc_em_version(int arcver, char *name, int name_len)
+{
+ const char *arc_name = "EM";
+ const char *arc_ver;
+ bool cache = ARC_FEATURE_EXISTS(ARC_BCR_IC_BUILD);
+ bool dsp = ARC_FEATURE_EXISTS(ARC_AUX_DSP_BUILD);
+ bool xymem = ARC_FEATURE_EXISTS(ARC_AUX_XY_BUILD);
+ int i;
+
+ for (i = 0; i++ < sizeof(em_versions) / sizeof(struct em_template_t);) {
+ if (em_versions[i].cache == cache &&
+ em_versions[i].dsp == dsp &&
+ em_versions[i].xymem == xymem) {
+ arc_name = em_versions[i].name;
+ break;
+ }
+ }
+
+ switch (arcver) {
+ case 0x41:
+ arc_ver = "v1.1a";
+ break;
+ case 0x42:
+ arc_ver = "v3.0";
+ break;
+ case 0x43:
+ arc_ver = "v4.0";
+ break;
+ case 0x44:
+ arc_ver = "v5.0";
+ break;
+ default:
+ arc_ver = "unknown version";
+ }
+
+ snprintf(name, name_len, "ARC %s %s", arc_name, arc_ver);
+
+ return name;
+}
+
+struct hs_template_t {
+ const bool cache;
+ const bool mmu;
+ const bool dual_issue;
+ const bool dsp;
+ const char name[8];
+};
+
+static const struct hs_template_t hs_versions[] = {
+ {false, false, false, false, "HS34"},
+ {true, false, false, false, "HS36"},
+ {true, true, false, false, "HS38"},
+ {false, false, true, false, "HS44"},
+ {true, false, true, false, "HS46"},
+ {true, true, true, false, "HS48"},
+ {false, false, true, true, "HS45D"},
+ {true, false, true, true, "HS47D"},
+};
+
+const char *arc_hs_version(int arcver, char *name, int name_len)
+{
+ const char *arc_name = "HS";
+ const char *arc_ver;
+ bool cache = ARC_FEATURE_EXISTS(ARC_BCR_IC_BUILD);
+ bool dsp = ARC_FEATURE_EXISTS(ARC_AUX_DSP_BUILD);
+ bool mmu = !!read_aux_reg(ARC_AUX_MMU_BCR);
+ bool dual_issue = arcver == 0x54 ? true : false;
+ int i;
+
+ for (i = 0; i++ < sizeof(hs_versions) / sizeof(struct hs_template_t);) {
+ if (hs_versions[i].cache == cache &&
+ hs_versions[i].mmu == mmu &&
+ hs_versions[i].dual_issue == dual_issue &&
+ hs_versions[i].dsp == dsp) {
+ arc_name = hs_versions[i].name;
+ break;
+ }
+ }
switch (arcver) {
- /* ARCompact cores */
- case 0x32: return "ARC 700 v4.4-4.5";
- case 0x33: return "ARC 700 v4.6-v4.9";
- case 0x34: return "ARC 700 v4.10";
- case 0x35: return "ARC 700 v4.11";
-
- /* ARCv2 cores */
- case 0x41: return "ARC EM v1.1a";
- case 0x42: return "ARC EM v3.0";
- case 0x43: return "ARC EM v4.0";
- case 0x50: return "ARC HS v1.0";
- case 0x51: return "ARC EM v2.0";
- case 0x52: return "ARC EM v2.1";
- case 0x53: return "ARC HS v3.0";
- case 0x54: return "ARC HS v4.0";
-
- default: return "Unknown ARC core";
+ case 0x50:
+ arc_ver = "v1.0";
+ break;
+ case 0x51:
+ arc_ver = "v2.0";
+ break;
+ case 0x52:
+ arc_ver = "v2.1c";
+ break;
+ case 0x53:
+ arc_ver = "v3.0";
+ break;
+ case 0x54:
+ arc_ver = "v4.0";
+ break;
+ default:
+ arc_ver = "unknown version";
}
+
+ snprintf(name, name_len, "ARC %s %s", arc_name, arc_ver);
+
+ return name;
+}
+
+const char *decode_identity(void)
+{
+#define MAX_CPU_NAME_LEN 64
+
+ int arcver = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
+ char *name = malloc(MAX_CPU_NAME_LEN);
+
+ if (arcver >= 0x50)
+ return arc_hs_version(arcver, name, MAX_CPU_NAME_LEN);
+ else if (arcver >= 0x40)
+ return arc_em_version(arcver, name, MAX_CPU_NAME_LEN);
+ else if (arcver >= 0x30)
+ return arc_700_version(arcver, name, MAX_CPU_NAME_LEN);
+ else
+ return "Unknown ARC core";
+}
+
+const char *decode_subsystem(void)
+{
+ int subsys_type = read_aux_reg(ARC_AUX_SUBSYS_BUILD) & GENMASK(3, 0);
+
+ switch (subsys_type) {
+ case 0: return NULL;
+ case 2: return "ARC Sensor & Control IP Subsystem";
+ case 3: return "ARC Data Fusion IP Subsystem";
+ case 4: return "ARC Secure Subsystem";
+ default: return "Unknown subsystem";
+ };
}
__weak int print_cpuinfo(void)
{
- printf("CPU: %s\n", decode_identity());
+ const char *subsys_name = decode_subsystem();
+ char mhz[8];
+
+ printf("CPU: %s at %s MHz\n", decode_identity(),
+ strmhz(mhz, gd->cpu_clk));
+
+ if (subsys_name)
+ printf("Subsys:%s\n", subsys_name);
+
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
--- /dev/null
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * VScom OnRISC
+ * http://www.vscom.de
+ */
+
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "OnRISC Baltos";
+ compatible = "vscom,onrisc", "ti,am33xx";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&vdd1_reg>;
+ };
+ };
+
+ vbat: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ };
+};
+
+&am33xx_pinmux {
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ 0xf0 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat3.mmc0_dat3 */
+ 0xf4 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat2.mmc0_dat2 */
+ 0xf8 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat1.mmc0_dat1 */
+ 0xfc (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat0.mmc0_dat0 */
+ 0x100 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_clk.mmc0_clk */
+ 0x104 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_cmd.mmc0_cmd */
+ >;
+ };
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ 0x158 0x2a /* spi0_d1.i2c1_sda_mux3, INPUT | MODE2 */
+ 0x15c 0x2a /* spi0_cs0.i2c1_scl_mux3, INPUT | MODE2 */
+ >;
+ };
+
+ tps65910_pins: pinmux_tps65910_pins {
+ pinctrl-single,pins = <
+ 0x078 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */
+ >;
+
+ };
+ tca6416_pins: pinmux_tca6416_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */
+ >;
+ };
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
+ 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+ >;
+ };
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
+ 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */
+ 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
+ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
+ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */
+
+
+ /* Slave 2 */
+ 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
+ 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
+ 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
+ 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
+ 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
+ 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
+ 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
+ 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
+ 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
+ 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
+ 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
+ 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
+ >;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ /* Slave 1 reset value */
+ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+
+ /* Slave 2 reset value*/
+ 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
+ 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins = <
+ /* MDIO reset value */
+ 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ nandflash_pins_s0: nandflash_pins_s0 {
+ pinctrl-single,pins = <
+ 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
+ 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
+ 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
+ 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
+ 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
+ 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
+ 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
+ 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
+ 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
+ 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
+ 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
+ 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
+ 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
+ >;
+ };
+};
+
+&elm {
+ status = "okay";
+};
+
+&gpmc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&nandflash_pins_s0>;
+ ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
+ status = "okay";
+
+ nand@0,0 {
+ reg = <0 0 0>; /* CS0, offset 0 */
+ nand-bus-width = <8>;
+ ti,nand-ecc-opt = "bch8";
+ ti,nand-xfer-type = "polled";
+
+ gpmc,device-nand = "true";
+ gpmc,device-width = <1>;
+ gpmc,sync-clk-ps = <0>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <44>;
+ gpmc,cs-wr-off-ns = <44>;
+ gpmc,adv-on-ns = <6>;
+ gpmc,adv-rd-off-ns = <34>;
+ gpmc,adv-wr-off-ns = <44>;
+ gpmc,we-on-ns = <0>;
+ gpmc,we-off-ns = <40>;
+ gpmc,oe-on-ns = <0>;
+ gpmc,oe-off-ns = <54>;
+ gpmc,access-ns = <64>;
+ gpmc,rd-cycle-ns = <82>;
+ gpmc,wr-cycle-ns = <82>;
+ gpmc,wait-on-read = "true";
+ gpmc,wait-on-write = "true";
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <0>;
+ gpmc,clk-activation-ns = <0>;
+ gpmc,wait-monitoring-ns = <0>;
+ gpmc,wr-access-ns = <40>;
+ gpmc,wr-data-mux-bus-ns = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ elm_id = <&elm>;
+
+ boot@0 {
+ label = "SPL";
+ reg = <0x0 0x20000>;
+ };
+ boot@20000{
+ label = "SPL.backup1";
+ reg = <0x20000 0x20000>;
+ };
+ boot@40000 {
+ label = "SPL.backup2";
+ reg = <0x40000 0x20000>;
+ };
+ boot@60000 {
+ label = "SPL.backup3";
+ reg = <0x60000 0x20000>;
+ };
+ boot@80000 {
+ label = "u-boot";
+ reg = <0x80000 0x1e0000>;
+ };
+ boot@260000 {
+ label = "UBI";
+ reg = <0x260000 0xfda0000>;
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+
+ status = "okay";
+ clock-frequency = <1000>;
+
+ tps: tps@2d {
+ reg = <0x2d>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <28 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&tps65910_pins>;
+ };
+
+ at24@50 {
+ compatible = "at24,24c02";
+ pagesize = <8>;
+ reg = <0x50>;
+ };
+
+ tca6416: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <20 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&tca6416_pins>;
+ };
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb_ctrl_mod {
+ status = "okay";
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&cppi41dma {
+ status = "okay";
+};
+
+/include/ "tps65910.dtsi"
+
+&tps {
+ vcc1-supply = <&vbat>;
+ vcc2-supply = <&vbat>;
+ vcc3-supply = <&vbat>;
+ vcc4-supply = <&vbat>;
+ vcc5-supply = <&vbat>;
+ vcc6-supply = <&vbat>;
+ vcc7-supply = <&vbat>;
+ vccio-supply = <&vbat>;
+
+ ti,en-ck32k-xtal = <1>;
+
+ regulators {
+ vrtc_reg: regulator@0 {
+ regulator-always-on;
+ };
+
+ vio_reg: regulator@1 {
+ regulator-always-on;
+ };
+
+ vdd1_reg: regulator@2 {
+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1312500>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd2_reg: regulator@3 {
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd3_reg: regulator@4 {
+ regulator-always-on;
+ };
+
+ vdig1_reg: regulator@5 {
+ regulator-always-on;
+ };
+
+ vdig2_reg: regulator@6 {
+ regulator-always-on;
+ };
+
+ vpll_reg: regulator@7 {
+ regulator-always-on;
+ };
+
+ vdac_reg: regulator@8 {
+ regulator-always-on;
+ };
+
+ vaux1_reg: regulator@9 {
+ regulator-always-on;
+ };
+
+ vaux2_reg: regulator@10 {
+ regulator-always-on;
+ };
+
+ vaux33_reg: regulator@11 {
+ regulator-always-on;
+ };
+
+ vmmc_reg: regulator@12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+};
+
+&mac {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_default>;
+ pinctrl-1 = <&cpsw_sleep>;
+ dual_emac = <1>;
+
+ status = "okay";
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ pinctrl-1 = <&davinci_mdio_sleep>;
+
+ status = "okay";
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "rmii";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <7>;
+ phy-mode = "rgmii-txid";
+ dual_emac_res_vlan = <2>;
+};
+
+&phy_sel {
+ rmii-clock-ext = <1>;
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ vmmc-supply = <&vmmc_reg>;
+ status = "okay";
+};
+
+&gpio0 {
+ ti,no-reset-on-init;
+};
no-map;
};
+ /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved_alt: secmon@5000000 {
+ reg = <0x0 0x05000000 0x0 0x300000>;
+ no-map;
+ };
+
linux,cma {
compatible = "shared-dma-pool";
reusable;
- size = <0x0 0xbc00000>;
+ size = <0x0 0x10000000>;
alignment = <0x0 0x400000>;
linux,cma-default;
};
ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
sysctrl_AO: sys-ctrl@0 {
- compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
+ compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
reg = <0x0 0x0 0x0 0x100>;
pwrc_vpu: power-controller-vpu {
};
};
+ dmcbus: bus@c8838000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xc8838000 0x0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>;
+
+ canvas: video-lut@48 {
+ compatible = "amlogic,canvas";
+ reg = <0x0 0x48 0x0 0x14>;
+ };
+ };
+
hiubus: bus@c883c000 {
compatible = "simple-bus";
reg = <0x0 0xc883c000 0x0 0x2000>;
ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
sysctrl: system-controller@0 {
- compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
+ compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon";
reg = <0 0 0 0x400>;
};
sd_emmc_a: mmc@70000 {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
- reg = <0x0 0x70000 0x0 0x2000>;
+ reg = <0x0 0x70000 0x0 0x800>;
interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
sd_emmc_b: mmc@72000 {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
- reg = <0x0 0x72000 0x0 0x2000>;
+ reg = <0x0 0x72000 0x0 0x800>;
interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
sd_emmc_c: mmc@74000 {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
- reg = <0x0 0x74000 0x0 0x2000>;
+ reg = <0x0 0x74000 0x0 0x800>;
interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
+
+ /* CVBS is available on CON1 pin 36, disabled by default */
+ cvbs-connector {
+ compatible = "composite-video-connector";
+ status = "disabled";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+};
+
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
};
ðmac {
};
};
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
clock-names = "isfr", "iahb", "venci";
};
-&hiubus {
- clkc: clock-controller@0 {
+&sysctrl {
+ clkc: clock-controller {
compatible = "amlogic,gxbb-clkc";
#clock-cells = <1>;
- reg = <0x0 0x0 0x0 0x3db>;
};
};
};
};
- spi_pins: spi {
+ spi_pins: spi-pins {
mux {
groups = "spi_miso",
"spi_mosi",
<&clkc CLKID_SD_EMMC_A_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
+ resets = <&reset RESET_SD_EMMC_A>;
};
&sd_emmc_b {
<&clkc CLKID_SD_EMMC_B_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
+ resets = <&reset RESET_SD_EMMC_B>;
};
&sd_emmc_c {
<&clkc CLKID_SD_EMMC_C_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
+ resets = <&reset RESET_SD_EMMC_C>;
};
&spicc {
};
&uart_AO {
- clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+ clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
};
&uart_AO_B {
- clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+ clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
};
&apb {
mali: gpu@c0000 {
- compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
+ compatible = "amlogic,meson-gxl-mali", "arm,mali-450";
reg = <0x0 0xc0000 0x0 0x40000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
/ {
compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
- model = "Libre Technology CC";
+ model = "Libre Computer Board AML-S905X-CC";
aliases {
serial0 = &uart_AO;
bus-width = <4>;
cap-sd-highspeed;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
max-frequency = <100000000>;
disable-wp;
};
&usb2_phy0 {
- /*
- * HDMI_5V is also used as supply for the USB VBUS.
- */
- phy-supply = <&hdmi_5v>;
+ /*
+ * HDMI_5V is also used as supply for the USB VBUS.
+ */
+ phy-supply = <&hdmi_5v>;
};
/ {
compatible = "amlogic,meson-gxl";
- reserved-memory {
- /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
- secmon_reserved_alt: secmon@5000000 {
- reg = <0x0 0x05000000 0x0 0x300000>;
- no-map;
- };
- };
-
soc {
usb0: usb@c9000000 {
status = "disabled";
clock-names = "isfr", "iahb", "venci";
};
-&hiubus {
- clkc: clock-controller@0 {
- compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
+&sysctrl {
+ clkc: clock-controller {
+ compatible = "amlogic,gxl-clkc";
#clock-cells = <1>;
- reg = <0x0 0x0 0x0 0x3db>;
};
};
};
};
- spi_pins: spi {
+ spi_pins: spi-pins {
mux {
groups = "spi_miso",
"spi_mosi",
<&clkc CLKID_SD_EMMC_A_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
+ resets = <&reset RESET_SD_EMMC_A>;
};
&sd_emmc_b {
clocks = <&clkc CLKID_SD_EMMC_B>,
<&clkc CLKID_SD_EMMC_B_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
- clock-names = "core", "clkin0", "clkin1";
+ clock-names = "core", "clkin0", "clkin1";
+ resets = <&reset RESET_SD_EMMC_B>;
};
&sd_emmc_c {
<&clkc CLKID_SD_EMMC_C_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
+ resets = <&reset RESET_SD_EMMC_C>;
};
&spicc {
};
&uart_AO {
- clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+ clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
};
&uart_AO_B {
- clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+ clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
};
#cooling-cells = <2>;
};
+&cpu1 {
+ #cooling-cells = <2>;
+};
+
+&cpu2 {
+ #cooling-cells = <2>;
+};
+
+&cpu3 {
+ #cooling-cells = <2>;
+};
+
&cpu4 {
#cooling-cells = <2>;
};
+&cpu5 {
+ #cooling-cells = <2>;
+};
+
+&cpu6 {
+ #cooling-cells = <2>;
+};
+
+&cpu7 {
+ #cooling-cells = <2>;
+};
+
ðmac {
pinctrl-0 = <ð_pins>;
pinctrl-names = "default";
ori r2, r2, CONFIG_SYS_DER@l
mtspr DER, r2
- /* set up the stack in internal DPRAM */
+ /* set up the stack on top of internal DPRAM */
lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
+ stw r0, -4(r3)
+ stw r0, -8(r3)
addi r1, r3, -8
bl board_init_f_alloc_reserve
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
+dtb-$(CONFIG_MCR3000) += mcr3000.dtb
targets += $(dtb-y)
--- /dev/null
+/*
+ * MCR3000 Device Tree Source
+ *
+ * Copyright 2017 CS Systemes d'Information
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+ WDT: watchdog@0 {
+ compatible = "fsl,pq1-wdt";
+ };
+ SERIAL: smc@0 {
+ compatible = "fsl,pq1-smc";
+ };
+
+ chosen {
+ stdout-path = &SERIAL;
+ };
+};
#include <mpc8xx.h>
#include <fdt_support.h>
#include <asm/io.h>
+#include <dm/uclass.h>
+#include <wdt.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+
+int board_early_init_r(void)
+{
+ struct udevice *watchdog_dev = NULL;
+
+ if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
+ puts("Cannot find watchdog!\n");
+ } else {
+ puts("Enabling watchdog.\n");
+ wdt_start(watchdog_dev, 0xffff, 0);
+ }
+
+ return 0;
+}
arch/powerpc/cpu/mpc8xx/start.o (.text)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
arch/powerpc/lib/built-in.o (.text*)
- board/cssi/MCR3000/built-in.o (.text*)
drivers/net/built-in.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
+ /*
+ * _end - This is end of u-boot.bin image.
+ * dtb will be appended here to make u-boot-dtb.bin
+ */
+ _end = .;
+
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
writel(cmd, (void __iomem *)AXC003_CREG_CPU_START);
}
#endif
+
+int checkboard(void)
+{
+ printf("Board: ARC Software Development Platform AXS%s\n",
+ is_isa_arcv2() ? "103" : "101");
+
+ return 0;
+};
#include <dwmmc.h>
#include <malloc.h>
+#include <asm/arcregs.h>
+
DECLARE_GLOBAL_DATA_PTR;
-#define ARC_PERIPHERAL_BASE 0xF0000000
-#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0x10000)
+#define ARC_PERIPHERAL_BASE 0xF0000000
+
+#define CGU_ARC_FMEAS_ARC (void *)(ARC_PERIPHERAL_BASE + 0x84)
+#define CGU_ARC_FMEAS_ARC_START BIT(31)
+#define CGU_ARC_FMEAS_ARC_DONE BIT(30)
+#define CGU_ARC_FMEAS_ARC_CNT_MASK GENMASK(14, 0)
+#define CGU_ARC_FMEAS_ARC_RCNT_OFFSET 0
+#define CGU_ARC_FMEAS_ARC_FCNT_OFFSET 15
+
+#define SDIO_BASE (void *)(ARC_PERIPHERAL_BASE + 0x10000)
+
+int mach_cpu_init(void)
+{
+ int rcnt, fcnt;
+ u32 data;
+
+ /* Start frequency measurement */
+ writel(CGU_ARC_FMEAS_ARC_START, CGU_ARC_FMEAS_ARC);
+
+ /* Poll DONE bit */
+ do {
+ data = readl(CGU_ARC_FMEAS_ARC);
+ } while (!(data & CGU_ARC_FMEAS_ARC_DONE));
+
+ /* Amount of reference 100 MHz clocks */
+ rcnt = ((data >> CGU_ARC_FMEAS_ARC_RCNT_OFFSET) &
+ CGU_ARC_FMEAS_ARC_CNT_MASK);
+
+ /* Amount of CPU clocks */
+ fcnt = ((data >> CGU_ARC_FMEAS_ARC_FCNT_OFFSET) &
+ CGU_ARC_FMEAS_ARC_CNT_MASK);
+
+ gd->cpu_clk = ((100 * fcnt) / rcnt) * 1000000;
+
+ return 0;
+}
int board_mmc_init(bd_t *bis)
{
memset(host, 0, sizeof(struct dwmci_host));
host->name = "Synopsys Mobile storage";
- host->ioaddr = (void *)SDIO_BASE;
+ host->ioaddr = SDIO_BASE;
host->buswidth = 4;
host->dev_index = 0;
host->bus_hz = 50000000;
}
#define CREG_BASE 0xF0001000
-#define CREG_BOOT_OFFSET 0
-#define CREG_BOOT_WP_OFFSET 8
+#define CREG_BOOT (void *)(CREG_BASE + 0x0FF0)
+#define CREG_IP_SW_RESET (void *)(CREG_BASE + 0x0FF0)
+#define CREG_IP_VERSION (void *)(CREG_BASE + 0x0FF8)
-#define CGU_BASE 0xF0000000
-#define CGU_IP_SW_RESET 0x0FF0
+/* Bits in CREG_BOOT register */
+#define CREG_BOOT_WP_BIT BIT(8)
void reset_cpu(ulong addr)
{
- writel(1, (u32 *)(CGU_BASE + CGU_IP_SW_RESET));
+ writel(1, CREG_IP_SW_RESET);
while (1)
; /* loop forever till reset */
}
static int do_emsdp_rom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
- u32 creg_boot = readl((u32 *)(CREG_BASE + CREG_BOOT_OFFSET));
+ u32 creg_boot = readl(CREG_BOOT);
if (!strcmp(argv[1], "unlock"))
- creg_boot &= ~BIT(CREG_BOOT_WP_OFFSET);
+ creg_boot &= ~CREG_BOOT_WP_BIT;
else if (!strcmp(argv[1], "lock"))
- creg_boot |= BIT(CREG_BOOT_WP_OFFSET);
+ creg_boot |= CREG_BOOT_WP_BIT;
else
return CMD_RET_USAGE;
- writel(creg_boot, (u32 *)(CREG_BASE + CREG_BOOT_OFFSET));
+ writel(creg_boot, CREG_BOOT);
return CMD_RET_SUCCESS;
}
"rom unlock - Unlock non-volatile memory for writing\n"
"emsdp rom lock - Lock non-volatile memory to prevent writing\n"
);
+
+int checkboard(void)
+{
+ int version = readl(CREG_IP_VERSION);
+
+ printf("Board: ARC EM Software Development Platform v%d.%d\n",
+ (version >> 16) & 0xff, version & 0xff);
+ return 0;
+};
return 0;
}
-#ifdef CONFIG_DISPLAY_CPUINFO
-int print_cpuinfo(void)
+int checkboard(void)
{
- printf("CPU: ARC HS38 v2.1c\n");
+ puts("Board: Synopsys ARC HS Development Kit\n");
return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
+};
puts("Board: Synopsys IoT Development Kit\n");
return 0;
};
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-int print_cpuinfo(void)
-{
- char mhz[8];
-
- printf("CPU: ARC EM9D at %s MHz\n", strmhz(mhz, gd->cpu_clk));
- return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
-#include <power/tps65217.h>
#include <power/tps65910.h>
#include <environment.h>
#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
-/* GPIO that controls power to DDR on EVM-SK */
-#define GPIO_DDR_VTT_EN 7
+/* GPIO that controls DIP switch and mPCIe slot */
#define DIP_S1 44
#define MPCIE_SW 100
void sdram_init(void)
{
- gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
- gpio_direction_output(GPIO_DDR_VTT_EN, 1);
-
config_ddr(400, &ioregs_baltos,
&ddr3_baltos_data,
&ddr3_baltos_cmd_ctrl_data,
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
- //{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
{-1},
};
{-1},
};
-static struct module_pin_mux gpio0_7_pin_mux[] = {
- {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
- {-1},
-};
-
static struct module_pin_mux rmii1_pin_mux[] = {
{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
{OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */
void enable_board_pin_mux()
{
configure_module_pin_mux(i2c1_pin_mux);
- configure_module_pin_mux(gpio0_7_pin_mux);
configure_module_pin_mux(rgmii2_pin_mux);
configure_module_pin_mux(rmii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
spi_write(addr, alen, buffer, len);
#else /* I2C */
+#if defined(CONFIG_DM_I2C) && defined(CONFIG_SYS_I2C_EEPROM_BUS)
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_EEPROM_BUS, addr[0],
+ alen - 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find udev for a bus %d\n", __func__,
+ CONFIG_SYS_I2C_EEPROM_BUS);
+ return CMD_RET_FAILURE;
+ }
+
+ if (read)
+ ret = dm_i2c_read(dev, offset, buffer, len);
+ else
+ ret = dm_i2c_write(dev, offset, buffer, len);
+
+#else /* Non DM I2C support - will be removed */
#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
#endif
ret = i2c_read(addr[0], offset, alen - 1, buffer, len);
else
ret = i2c_write(addr[0], offset, alen - 1, buffer, len);
-
- if (ret)
- ret = 1;
#endif
+#endif /* CONFIG_DM_I2C && CONFIG_SYS_I2C_EEPROM_BUS */
+ if (ret)
+ ret = CMD_RET_FAILURE;
+
return ret;
}
/* initialize higher level parts of CPU like time base and timers */
cpu_init_r,
#endif
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) && !defined(CONFIG_DM_SPI)
initr_spi,
#endif
#ifdef CONFIG_CMD_NAND
uint8_t *value;
int value_len;
char *algo;
+ const char *padding;
int required;
int ret, i;
printf(" (required)");
printf("\n");
+ padding = fdt_getprop(fit, noffset, "padding", NULL);
+ if (padding)
+ printf("%s %s padding: %s\n", p, type, padding);
+
ret = fit_image_hash_get_value(fit, noffset, &value,
&value_len);
printf("%s %s value: ", p, type);
};
+struct padding_algo padding_algos[] = {
+ {
+ .name = "pkcs-1.5",
+ .verify = padding_pkcs_15_verify,
+ },
+#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT
+ {
+ .name = "pss",
+ .verify = padding_pss_verify,
+ }
+#endif /* CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT */
+};
+
struct checksum_algo *image_get_checksum_algo(const char *full_name)
{
int i;
return NULL;
}
+struct padding_algo *image_get_padding_algo(const char *name)
+{
+ int i;
+
+ if (!name)
+ return NULL;
+
+ for (i = 0; i < ARRAY_SIZE(padding_algos); i++) {
+ if (!strcmp(padding_algos[i].name, name))
+ return &padding_algos[i];
+ }
+
+ return NULL;
+}
+
/**
* fit_region_make_list() - Make a list of image regions
*
char **err_msgp)
{
char *algo_name;
+ const char *padding_name;
if (fdt_totalsize(fit) > CONFIG_FIT_SIGNATURE_MAX_SIZE) {
*err_msgp = "Total size too large";
*err_msgp = "Can't get hash algo property";
return -1;
}
+
+ padding_name = fdt_getprop(fit, noffset, "padding", NULL);
+ if (!padding_name)
+ padding_name = RSA_DEFAULT_PADDING_NAME;
+
memset(info, '\0', sizeof(*info));
info->keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL);
info->fit = (void *)fit;
info->name = algo_name;
info->checksum = image_get_checksum_algo(algo_name);
info->crypto = image_get_crypto_algo(algo_name);
+ info->padding = image_get_padding_algo(padding_name);
info->fdt_blob = gd_fdt_blob();
info->required_keynode = required_keynode;
printf("%s:%s", algo_name, info->keyname);
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run flashboot"
CONFIG_MISC_INIT_R=y
+CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="S3K> "
CONFIG_SHA256=y
CONFIG_LZMA=y
CONFIG_OF_LIBFDT=y
+CONFIG_DM=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="mcr3000"
+CONFIG_WDT=y
+CONFIG_WDT_MPC8xx=y
+CONFIG_DM_SERIAL=y
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_AM33XX=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(SPL),128k(SPL.backup1),128k(SPL.backup2),128k(SPL.backup3),1920k(u-boot),-(UBI)"
CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-baltos"
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_OMAP24_I2C_SPEED=1000
+CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_MMC_OMAP_HS_ADMA=y
CONFIG_NAND=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x00080000
CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_DRIVER_TI_CPSW=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_SMSC=y
CONFIG_MII=y
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_GADGET_VENDOR_NUM=0x0403
CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_USB_ETHER=y
CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_MII=y
+CONFIG_RTC_M41T62=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_SPI=y
CONFIG_NAND_MXC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_RTC_M41T62=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_MII=y
+CONFIG_RTC_M41T62=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
+CONFIG_RTC_M41T62=y
CONFIG_CONS_INDEX=0
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
- comment: Additional information about the signer or image
+- padding: The padding algorithm, it may be pkcs-1.5 or pss,
+ if no value is provided we assume pkcs-1.5
+
For config bindings (see Signed Configurations below), the following
additional properties are optional:
#include <clk-uclass.h>
#include <div64.h>
#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
#include <dt-bindings/clock/gxbb-clkc.h>
#include "clk_meson.h"
#define XTAL_RATE 24000000
struct meson_clk {
- void __iomem *addr;
+ struct regmap *map;
};
static ulong meson_div_get_rate(struct clk *clk, unsigned long id);
debug("%s: really %sabling %ld\n", __func__, on ? "en" : "dis", id);
- clrsetbits_le32(priv->addr + gate->reg,
- BIT(gate->bit), on ? BIT(gate->bit) : 0);
+ regmap_update_bits(priv->map, gate->reg,
+ BIT(gate->bit), on ? BIT(gate->bit) : 0);
/* Propagate to next gate(s) */
switch (id) {
unsigned int rate, parent_rate;
struct parm *parm;
int parent;
- u32 reg;
+ uint reg;
switch (id) {
case CLKID_VPU_0_DIV:
return -ENOENT;
}
- reg = readl(priv->addr + parm->reg_off);
+ regmap_read(priv->map, parm->reg_off, ®);
reg = PARM_GET(parm->width, parm->shift, reg);
debug("%s: div of %ld is %d\n", __func__, id, reg + 1);
unsigned long parent_rate;
struct parm *parm;
int parent;
- u32 reg;
int ret;
if (current_rate == rate)
debug("%s: setting div of %ld to %d\n", __func__, id, new_div);
- reg = readl(priv->addr + parm->reg_off);
- writel(PARM_SET(parm->width, parm->shift, reg, new_div - 1),
- priv->addr + parm->reg_off);
+ regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),
+ (new_div - 1) << parm->shift);
debug("%s: new rate of %ld is %ld\n",
__func__, id, meson_div_get_rate(clk, id));
struct meson_clk *priv = dev_get_priv(clk->dev);
struct parm *parm;
int *parents;
- u32 reg;
+ uint reg;
switch (id) {
case CLKID_VPU:
return -ENOENT;
}
- reg = readl(priv->addr + parm->reg_off);
+ regmap_read(priv->map, parm->reg_off, ®);
reg = PARM_GET(parm->width, parm->shift, reg);
debug("%s: parent of %ld is %d (%d)\n",
unsigned int new_index = -EINVAL;
struct parm *parm;
int *parents;
- u32 reg;
int i;
if (IS_ERR_VALUE(cur_parent))
debug("%s: new index of %ld is %d\n", __func__, id, new_index);
- reg = readl(priv->addr + parm->reg_off);
- writel(PARM_SET(parm->width, parm->shift, reg, new_index),
- priv->addr + parm->reg_off);
+ regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),
+ new_index << parm->shift);
debug("%s: new parent of %ld is %ld\n",
__func__, id, meson_mux_get_parent(clk, id));
{
struct meson_clk *priv = dev_get_priv(clk->dev);
unsigned long parent_rate;
- u32 reg;
+ uint reg;
int parents[] = {
-1,
-1,
};
/* mux */
- reg = readl(priv->addr + HHI_MPEG_CLK_CNTL);
+ regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
reg = (reg >> 12) & 7;
switch (reg) {
}
/* divider */
- reg = readl(priv->addr + HHI_MPEG_CLK_CNTL);
+ regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
reg = reg & ((1 << 7) - 1);
/* clk81 divider is zero based */
{
struct meson_clk *priv = dev_get_priv(clk->dev);
struct parm *psdm, *pn2;
- unsigned long reg, sdm, n2;
+ unsigned long sdm, n2;
unsigned long parent_rate;
+ uint reg;
switch (id) {
case CLKID_MPLL0:
if (IS_ERR_VALUE(parent_rate))
return parent_rate;
- reg = readl(priv->addr + psdm->reg_off);
+ regmap_read(priv->map, psdm->reg_off, ®);
sdm = PARM_GET(psdm->width, psdm->shift, reg);
- reg = readl(priv->addr + pn2->reg_off);
+ regmap_read(priv->map, pn2->reg_off, ®);
n2 = PARM_GET(pn2->width, pn2->shift, reg);
return mpll_rate_from_params(parent_rate, sdm, n2);
struct parm *pm, *pn, *pod;
unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
u16 n, m, od;
- u32 reg;
+ uint reg;
switch (id) {
case CLKID_FIXED_PLL:
return -ENOENT;
}
- reg = readl(priv->addr + pn->reg_off);
+ regmap_read(priv->map, pn->reg_off, ®);
n = PARM_GET(pn->width, pn->shift, reg);
- reg = readl(priv->addr + pm->reg_off);
+ regmap_read(priv->map, pm->reg_off, ®);
m = PARM_GET(pm->width, pm->shift, reg);
- reg = readl(priv->addr + pod->reg_off);
+ regmap_read(priv->map, pod->reg_off, ®);
od = PARM_GET(pod->width, pod->shift, reg);
return ((parent_rate_mhz * m / n) >> od) * 1000000;
if (IS_ERR_VALUE(ret))
return ret;
- printf("clock %lu has new rate %lu\n", clk->id,
- meson_clk_get_rate_by_id(clk, clk->id));
+ debug("clock %lu has new rate %lu\n", clk->id,
+ meson_clk_get_rate_by_id(clk, clk->id));
return 0;
}
{
struct meson_clk *priv = dev_get_priv(dev);
- priv->addr = dev_read_addr_ptr(dev);
+ priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
+ if (IS_ERR(priv->map))
+ return PTR_ERR(priv->map);
- debug("meson-clk: probed at addr %p\n", priv->addr);
+ debug("meson-clk: probed\n");
return 0;
}
clock with a wide array of features and 50 bytes of general-purpose,
battery-backed RAM. The driver supports access to the clock and RAM.
+config RTC_M41T62
+ bool "Enable M41T62 driver"
+ help
+ Enable driver for ST's M41T62 compatible RTC devices (like RV-4162).
+ It is a serial (I2C) real-time clock (RTC) with alarm.
+
endmenu
// SPDX-License-Identifier: GPL-2.0+
/*
+ * (C) Copyright 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
+ *
* (C) Copyright 2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
#include <common.h>
#include <command.h>
+#include <dm.h>
#include <rtc.h>
#include <i2c.h>
#define M41T80_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */
-int rtc_get(struct rtc_time *tm)
+static void m41t62_update_rtc_time(struct rtc_time *tm, u8 *buf)
{
- u8 buf[M41T62_DATETIME_REG_SIZE];
-
- i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
-
debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
__FUNCTION__,
__FUNCTION__,
tm->tm_sec, tm->tm_min, tm->tm_hour,
tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
-
- return 0;
}
-int rtc_set(struct rtc_time *tm)
+static void m41t62_set_rtc_buf(const struct rtc_time *tm, u8 *buf)
{
- u8 buf[M41T62_DATETIME_REG_SIZE];
-
debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
tm->tm_hour, tm->tm_min, tm->tm_sec);
- i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
-
/* Merge time-data and register flags into buf[0..7] */
buf[M41T62_REG_SSEC] = 0;
buf[M41T62_REG_SEC] =
bin2bcd(tm->tm_mon) | (buf[M41T62_REG_MON] & ~0x1f);
/* assume 20YY not 19YY */
buf[M41T62_REG_YEAR] = bin2bcd(tm->tm_year % 100);
+}
+
+#ifdef CONFIG_DM_RTC
+static int m41t62_rtc_get(struct udevice *dev, struct rtc_time *tm)
+{
+ u8 buf[M41T62_DATETIME_REG_SIZE];
+ int ret;
+
+ ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
+ if (ret)
+ return ret;
+
+ m41t62_update_rtc_time(tm, buf);
+
+ return 0;
+}
+
+static int m41t62_rtc_set(struct udevice *dev, const struct rtc_time *tm)
+{
+ u8 buf[M41T62_DATETIME_REG_SIZE];
+ int ret;
+
+ ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
+ if (ret)
+ return ret;
+
+ m41t62_set_rtc_buf(tm, buf);
+
+ ret = dm_i2c_write(dev, 0, buf, sizeof(buf));
+ if (ret) {
+ printf("I2C write failed in %s()\n", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int m41t62_rtc_reset(struct udevice *dev)
+{
+ u8 val;
+
+ /*
+ * M41T82: Make sure HT (Halt Update) bit is cleared.
+ * This bit is 0 in M41T62 so its save to clear it always.
+ */
+
+ int ret = dm_i2c_read(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
+
+ val &= ~M41T80_ALHOUR_HT;
+ ret |= dm_i2c_write(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
+
+ return ret;
+}
+
+static const struct rtc_ops m41t62_rtc_ops = {
+ .get = m41t62_rtc_get,
+ .set = m41t62_rtc_set,
+ .reset = m41t62_rtc_reset,
+};
+
+static const struct udevice_id m41t62_rtc_ids[] = {
+ { .compatible = "st,m41t62" },
+ { .compatible = "microcrystal,rv4162" },
+ { }
+};
+
+U_BOOT_DRIVER(rtc_m41t62) = {
+ .name = "rtc-m41t62",
+ .id = UCLASS_RTC,
+ .of_match = m41t62_rtc_ids,
+ .ops = &m41t62_rtc_ops,
+};
+
+#else /* NON DM RTC code - will be removed */
+int rtc_get(struct rtc_time *tm)
+{
+ u8 buf[M41T62_DATETIME_REG_SIZE];
+
+ i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
+ m41t62_update_rtc_time(tm, buf);
+
+ return 0;
+}
+
+int rtc_set(struct rtc_time *tm)
+{
+ u8 buf[M41T62_DATETIME_REG_SIZE];
+
+ i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
+ m41t62_set_rtc_buf(tm, buf);
- if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE)) {
+ if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf,
+ M41T62_DATETIME_REG_SIZE)) {
printf("I2C write failed in %s()\n", __func__);
return -1;
}
val &= ~M41T80_ALHOUR_HT;
i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
}
+#endif /* CONFIG_DM_RTC */
serial_initfunc(atmel_serial_initialize);
serial_initfunc(mcf_serial_initialize);
serial_initfunc(mpc85xx_serial_initialize);
-serial_initfunc(mpc8xx_serial_initialize);
serial_initfunc(mxc_serial_initialize);
serial_initfunc(ns16550_serial_initialize);
serial_initfunc(pl01x_serial_initialize);
atmel_serial_initialize();
mcf_serial_initialize();
mpc85xx_serial_initialize();
- mpc8xx_serial_initialize();
mxc_serial_initialize();
ns16550_serial_initialize();
pl01x_serial_initialize();
#include <common.h>
#include <command.h>
+#include <dm.h>
#include <serial.h>
#include <watchdog.h>
#include <asm/cpm_8xx.h>
uchar txbuf; /* tx buffers */
};
-static void serial_setdivisor(cpm8xx_t __iomem *cp)
+static void serial_setdivisor(cpm8xx_t __iomem *cp, int baudrate)
{
- int divisor = (gd->cpu_clk + 8 * gd->baudrate) / 16 / gd->baudrate;
+ int divisor = (gd->cpu_clk + 8 * baudrate) / 16 / baudrate;
if (divisor / 16 > 0x1000) {
/* bad divisor, assume 50MHz clock and 9600 baud */
* as serial console interface.
*/
-static void smc_setbrg(void)
+static int serial_mpc8xx_setbrg(struct udevice *dev, int baudrate)
{
immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cp = &(im->im_cpm);
out_be32(&cp->cp_simode, 0);
- serial_setdivisor(cp);
+ serial_setdivisor(cp, baudrate);
+
+ return 0;
}
-static int smc_init(void)
+static int serial_mpc8xx_probe(struct udevice *dev)
{
immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
smc_t __iomem *sp;
out_8(&sp->smc_smce, 0xff);
/* Set up the baud rate generator */
- smc_setbrg();
+ serial_mpc8xx_setbrg(dev, gd->baudrate);
/* Make the first buffer the only buffer. */
setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP);
return 0;
}
-static void smc_putc(const char c)
+static int serial_mpc8xx_putc(struct udevice *dev, const char c)
{
immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cpmp = &(im->im_cpm);
struct serialbuffer __iomem *rtx;
if (c == '\n')
- smc_putc('\r');
+ serial_mpc8xx_putc(dev, '\r');
rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
WATCHDOG_RESET();
-}
-static void smc_puts(const char *s)
-{
- while (*s)
- smc_putc(*s++);
+ return 0;
}
-static int smc_getc(void)
+static int serial_mpc8xx_getc(struct udevice *dev)
{
immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cpmp = &(im->im_cpm);
return c;
}
-static int smc_tstc(void)
+static int serial_mpc8xx_pending(struct udevice *dev, bool input)
{
immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cpmp = &(im->im_cpm);
struct serialbuffer __iomem *rtx;
+ if (!input)
+ return 0;
+
rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY);
}
-struct serial_device serial_smc_device = {
- .name = "serial_smc",
- .start = smc_init,
- .stop = NULL,
- .setbrg = smc_setbrg,
- .getc = smc_getc,
- .tstc = smc_tstc,
- .putc = smc_putc,
- .puts = smc_puts,
+static const struct dm_serial_ops serial_mpc8xx_ops = {
+ .putc = serial_mpc8xx_putc,
+ .pending = serial_mpc8xx_pending,
+ .getc = serial_mpc8xx_getc,
+ .setbrg = serial_mpc8xx_setbrg,
};
-__weak struct serial_device *default_serial_console(void)
-{
- return &serial_smc_device;
-}
+static const struct udevice_id serial_mpc8xx_ids[] = {
+ { .compatible = "fsl,pq1-smc" },
+ { }
+};
-void mpc8xx_serial_initialize(void)
-{
- serial_register(&serial_smc_device);
-}
+U_BOOT_DRIVER(serial_mpc8xx) = {
+ .name = "serial_mpc8xx",
+ .id = UCLASS_SERIAL,
+ .of_match = serial_mpc8xx_ids,
+ .probe = serial_mpc8xx_probe,
+ .ops = &serial_mpc8xx_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
*/
#include <common.h>
+#include <dm.h>
#include <mpc8xx.h>
+#include <spi.h>
+
#include <asm/cpm_8xx.h>
-#include <linux/ctype.h>
-#include <malloc.h>
-#include <post.h>
-#include <serial.h>
-
-#define SPI_EEPROM_WREN 0x06
-#define SPI_EEPROM_RDSR 0x05
-#define SPI_EEPROM_READ 0x03
-#define SPI_EEPROM_WRITE 0x02
-
-/* ---------------------------------------------------------------
- * Offset for initial SPI buffers in DPRAM:
- * We need a 520 byte scratch DPRAM area to use at an early stage.
- * It is used between the two initialization calls (spi_init_f()
- * and spi_init_r()).
- * The value 0xb00 makes it far enough from the start of the data
- * area (as well as from the stack pointer).
- * --------------------------------------------------------------- */
-#ifndef CONFIG_SYS_SPI_INIT_OFFSET
-#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
-#endif
+#include <asm/io.h>
#define CPM_SPI_BASE_RX CPM_SPI_BASE
#define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t))
-/* -------------------
- * Function prototypes
- * ------------------- */
-ssize_t spi_xfer(size_t);
-
-/* -------------------
- * Variables
- * ------------------- */
-
#define MAX_BUFFER 0x104
-/* ----------------------------------------------------------------------
- * Initially we place the RX and TX buffers at a fixed location in DPRAM!
- * ---------------------------------------------------------------------- */
-static uchar *rxbuf =
- (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
- [CONFIG_SYS_SPI_INIT_OFFSET];
-static uchar *txbuf =
- (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
- [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER];
-
-/* **************************************************************************
- *
- * Function: spi_init_f
- *
- * Description: Init SPI-Controller (ROM part)
- *
- * return: ---
- *
- * *********************************************************************** */
-void spi_init_f(void)
+static int mpc8xx_spi_probe(struct udevice *dev)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cp = &immr->im_cpm;
clrbits_be16(&tbdf->cbd_sc, BD_SC_READY);
clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY);
- /* Set the bd's rx and tx buffer address pointers */
- out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf);
- out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf);
-
/* 10 + 11 */
out_8(&cp->cp_spim, 0); /* Mask all SPI events */
out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
- return;
+ return 0;
}
-/* **************************************************************************
- *
- * Function: spi_init_r
- *
- * Description: Init SPI-Controller (RAM part) -
- * The malloc engine is ready and we can move our buffers to
- * normal RAM
- *
- * return: ---
- *
- * *********************************************************************** */
-void spi_init_r(void)
+static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cp = &immr->im_cpm;
- spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
- cbd_t __iomem *tbdf, *rbdf;
-
- /* Disable relocation */
- out_be16(&spi->spi_rpbase, 0);
-
- /* tx and rx buffer descriptors */
- tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
- rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
-
- /* Allocate memory for RX and TX buffers */
- rxbuf = (uchar *)malloc(MAX_BUFFER);
- txbuf = (uchar *)malloc(MAX_BUFFER);
-
- out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf);
- out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf);
-
- return;
-}
-
-/****************************************************************************
- * Function: spi_write
- **************************************************************************** */
-ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
-{
- int i;
-
- memset(rxbuf, 0, MAX_BUFFER);
- memset(txbuf, 0, MAX_BUFFER);
- *txbuf = SPI_EEPROM_WREN; /* write enable */
- spi_xfer(1);
- memcpy(txbuf, addr, alen);
- *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */
- memcpy(alen + txbuf, buffer, len);
- spi_xfer(alen + len);
- /* ignore received data */
- for (i = 0; i < 1000; i++) {
- *txbuf = SPI_EEPROM_RDSR; /* read status */
- txbuf[1] = 0;
- spi_xfer(2);
- if (!(rxbuf[1] & 1))
- break;
- udelay(1000);
- }
- if (i >= 1000)
- printf("*** spi_write: Time out while writing!\n");
-
- return len;
-}
-
-/****************************************************************************
- * Function: spi_read
- **************************************************************************** */
-ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
-{
- memset(rxbuf, 0, MAX_BUFFER);
- memset(txbuf, 0, MAX_BUFFER);
- memcpy(txbuf, addr, alen);
- *txbuf = SPI_EEPROM_READ; /* READ memory array */
-
- /*
- * There is a bug in 860T (?) that cuts the last byte of input
- * if we're reading into DPRAM. The solution we choose here is
- * to always read len+1 bytes (we have one extra byte at the
- * end of the buffer).
- */
- spi_xfer(alen + len + 1);
- memcpy(buffer, alen + rxbuf, len);
-
- return len;
-}
-
-/****************************************************************************
- * Function: spi_xfer
- **************************************************************************** */
-ssize_t spi_xfer(size_t count)
-{
- immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
- cpm8xx_t __iomem *cp = &immr->im_cpm;
- spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
cbd_t __iomem *tbdf, *rbdf;
int tm;
+ size_t count = (bitlen + 7) / 8;
- /* Disable relocation */
- out_be16(&spi->spi_rpbase, 0);
+ if (count > MAX_BUFFER)
+ return -EINVAL;
tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
clrbits_be32(&cp->cp_pbdat, 0x0001);
/* Setting tx bd status and data length */
+ out_be32(&tbdf->cbd_bufaddr, (ulong)dout);
out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP);
out_be16(&tbdf->cbd_datlen, count);
/* Setting rx bd status and data length */
+ out_be32(&rbdf->cbd_bufaddr, (ulong)din);
out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */
return count;
}
+
+static const struct dm_spi_ops mpc8xx_spi_ops = {
+ .xfer = mpc8xx_spi_xfer,
+};
+
+static const struct udevice_id mpc8xx_spi_ids[] = {
+ { .compatible = "fsl,mpc8xx-spi" },
+ { }
+};
+
+U_BOOT_DRIVER(mpc8xx_spi) = {
+ .name = "mpc8xx_spi",
+ .id = UCLASS_SPI,
+ .of_match = mpc8xx_spi_ids,
+ .ops = &mpc8xx_spi_ops,
+ .probe = mpc8xx_spi_probe,
+};
Select this to enable Ralink / Mediatek watchdog timer,
which can be found on some MediaTek chips.
+config WDT_MPC8xx
+ bool "MPC8xx watchdog timer support"
+ depends on WDT && MPC8xx
+ select CONFIG_MPC8xx_WATCHDOG
+ help
+ Select this to enable mpc8xx watchdog timer
+
endmenu
*/
#include <common.h>
+#include <dm.h>
+#include <wdt.h>
#include <mpc8xx.h>
#include <asm/cpm_8xx.h>
#include <asm/io.h>
out_be16(&immap->im_siu_conf.sc_swsr, 0xaa39); /* write magic2 */
}
+#ifdef CONFIG_WDT_MPC8xx
+static int mpc8xx_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ out_be32(&immap->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR);
+
+ if (!(in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE))
+ return -EBUSY;
+ return 0;
+
+}
+
+static int mpc8xx_wdt_stop(struct udevice *dev)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ out_be32(&immap->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE);
+
+ if (in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE)
+ return -EBUSY;
+ return 0;
+}
+
+static int mpc8xx_wdt_reset(struct udevice *dev)
+{
+ hw_watchdog_reset();
+
+ return 0;
+}
+
+static const struct wdt_ops mpc8xx_wdt_ops = {
+ .start = mpc8xx_wdt_start,
+ .reset = mpc8xx_wdt_reset,
+ .stop = mpc8xx_wdt_stop,
+};
+
+static const struct udevice_id mpc8xx_wdt_ids[] = {
+ { .compatible = "fsl,pq1-wdt" },
+ {}
+};
+
+U_BOOT_DRIVER(wdt_mpc8xx) = {
+ .name = "wdt_mpc8xx",
+ .id = UCLASS_WDT,
+ .of_match = mpc8xx_wdt_ids,
+ .ops = &mpc8xx_wdt_ops,
+};
+#endif /* CONFIG_WDT_MPC8xx */
/* FIT support */
#define CONFIG_SYS_BOOTM_LEN SZ_64M
-/* UBI Support */
-
-/* I2C configuration */
-
#ifdef CONFIG_NAND
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00080000
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
-#endif
+
#define NANDARGS \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
#define CONFIG_AM335X_USB1
#define CONFIG_AM335X_USB1_MODE MUSB_OTG
-/* Network. */
-#define CONFIG_PHY_SMSC
-#define CONFIG_PHY_ATHEROS
-
/* NAND support */
#ifdef CONFIG_NAND
#define GPMC_NAND_ECC_LP_x8_LAYOUT 1
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_SDRAM_BASE 0x10000000
-#define CONFIG_SYS_SDRAM_SIZE SZ_8M
+#define CONFIG_SYS_SDRAM_SIZE SZ_16M
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_1M)
* RTC
*/
#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_M41T62
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
#endif
#define CONFIG_SYS_I2C_MXC
/* RTC (actually an RV-4162 but M41T62-compatible) */
-#define CONFIG_RTC_M41T62
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_RTC_BUS_NUM 2
#define CONFIG_SYS_I2C_SLAVE 0x02
#define CONFIG_I2C_CHIPADDRESS 0x50
-#define CONFIG_RTC_M41T62 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
/* FPGA config options */
#define IMAGE_ENABLE_FIT 1
#define IMAGE_ENABLE_OF_LIBFDT 1
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT 1
#define CONFIG_FIT_ENABLE_SHA256_SUPPORT
#define CONFIG_SHA1
#define CONFIG_SHA256
int node_offset; /* Offset of signature node */
const char *name; /* Algorithm name */
struct checksum_algo *checksum; /* Checksum algorithm information */
+ struct padding_algo *padding; /* Padding algorithm information */
struct crypto_algo *crypto; /* Crypto algorithm information */
const void *fdt_blob; /* FDT containing public keys */
int required_keynode; /* Node offset of key to use: -1=any */
uint8_t *sig, uint sig_len);
};
+struct padding_algo {
+ const char *name;
+ int (*verify)(struct image_sign_info *info,
+ uint8_t *pad, int pad_len,
+ const uint8_t *hash, int hash_len);
+};
+
/**
* image_get_checksum_algo() - Look up a checksum algorithm
*
*/
struct crypto_algo *image_get_crypto_algo(const char *full_name);
+/**
+ * image_get_padding_algo() - Look up a padding algorithm
+ *
+ * @param name Name of padding algorithm
+ * @return pointer to algorithm information, or NULL if not found
+ */
+struct padding_algo *image_get_padding_algo(const char *name);
+
/**
* fit_image_verify_required_sigs() - Verify signatures marked as 'required'
*
void atmel_serial_initialize(void);
void mcf_serial_initialize(void);
void mpc85xx_serial_initialize(void);
-void mpc8xx_serial_initialize(void);
void mxc_serial_initialize(void);
void ns16550_serial_initialize(void);
void pl01x_serial_initialize(void);
int rsa_verify(struct image_sign_info *info,
const struct image_region region[], int region_count,
uint8_t *sig, uint sig_len);
+
+int padding_pkcs_15_verify(struct image_sign_info *info,
+ uint8_t *msg, int msg_len,
+ const uint8_t *hash, int hash_len);
+
+#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT
+int padding_pss_verify(struct image_sign_info *info,
+ uint8_t *msg, int msg_len,
+ const uint8_t *hash, int hash_len);
+#endif /* CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT */
#else
static inline int rsa_verify(struct image_sign_info *info,
const struct image_region region[], int region_count,
{
return -ENXIO;
}
+
+static inline int padding_pkcs_15_verify(struct image_sign_info *info,
+ uint8_t *msg, int msg_len,
+ const uint8_t *hash, int hash_len)
+{
+ return -ENXIO;
+}
+
+#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT
+static inline int padding_pss_verify(struct image_sign_info *info,
+ uint8_t *msg, int msg_len,
+ const uint8_t *hash, int hash_len)
+{
+ return -ENXIO;
+}
+#endif /* CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT */
#endif
+#define RSA_DEFAULT_PADDING_NAME "pkcs-1.5"
+
#define RSA2048_BYTES (2048 / 8)
#define RSA4096_BYTES (4096 / 8)
}
}
-static int rsa_sign_with_key(RSA *rsa, struct checksum_algo *checksum_algo,
+static int rsa_sign_with_key(RSA *rsa, struct padding_algo *padding_algo,
+ struct checksum_algo *checksum_algo,
const struct image_region region[], int region_count,
uint8_t **sigp, uint *sig_size)
{
EVP_PKEY *key;
+ EVP_PKEY_CTX *ckey;
EVP_MD_CTX *context;
- int size, ret = 0;
+ int ret = 0;
+ size_t size;
uint8_t *sig;
int i;
size = EVP_PKEY_size(key);
sig = malloc(size);
if (!sig) {
- fprintf(stderr, "Out of memory for signature (%d bytes)\n",
+ fprintf(stderr, "Out of memory for signature (%zu bytes)\n",
size);
ret = -ENOMEM;
goto err_alloc;
goto err_create;
}
EVP_MD_CTX_init(context);
- if (!EVP_SignInit(context, checksum_algo->calculate_sign())) {
+
+ ckey = EVP_PKEY_CTX_new(key, NULL);
+ if (!ckey) {
+ ret = rsa_err("EVP key context creation failed");
+ goto err_create;
+ }
+
+ if (EVP_DigestSignInit(context, &ckey,
+ checksum_algo->calculate_sign(),
+ NULL, key) <= 0) {
ret = rsa_err("Signer setup failed");
goto err_sign;
}
+#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT
+ if (padding_algo && !strcmp(padding_algo->name, "pss")) {
+ if (EVP_PKEY_CTX_set_rsa_padding(ckey,
+ RSA_PKCS1_PSS_PADDING) <= 0) {
+ ret = rsa_err("Signer padding setup failed");
+ goto err_sign;
+ }
+ }
+#endif /* CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT */
+
for (i = 0; i < region_count; i++) {
- if (!EVP_SignUpdate(context, region[i].data, region[i].size)) {
+ if (!EVP_DigestSignUpdate(context, region[i].data,
+ region[i].size)) {
ret = rsa_err("Signing data failed");
goto err_sign;
}
}
- if (!EVP_SignFinal(context, sig, sig_size, key)) {
+ if (!EVP_DigestSignFinal(context, sig, &size)) {
ret = rsa_err("Could not obtain signature");
goto err_sign;
}
+
#if OPENSSL_VERSION_NUMBER < 0x10100000L || \
(defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL)
EVP_MD_CTX_cleanup(context);
EVP_MD_CTX_destroy(context);
EVP_PKEY_free(key);
- debug("Got signature: %d bytes, expected %d\n", *sig_size, size);
+ debug("Got signature: %d bytes, expected %zu\n", *sig_size, size);
*sigp = sig;
*sig_size = size;
ret = rsa_get_priv_key(info->keydir, info->keyname, e, &rsa);
if (ret)
goto err_priv;
- ret = rsa_sign_with_key(rsa, info->checksum, region,
+ ret = rsa_sign_with_key(rsa, info->padding, info->checksum, region,
region_count, sigp, sig_len);
if (ret)
goto err_sign;
return ret;
}
+int padding_pkcs_15_verify(struct image_sign_info *info,
+ uint8_t *msg, int msg_len,
+ const uint8_t *hash, int hash_len)
+{
+ struct checksum_algo *checksum = info->checksum;
+ int ret, pad_len = msg_len - checksum->checksum_len;
+
+ /* Check pkcs1.5 padding bytes. */
+ ret = rsa_verify_padding(msg, pad_len, checksum);
+ if (ret) {
+ debug("In RSAVerify(): Padding check failed!\n");
+ return -EINVAL;
+ }
+
+ /* Check hash. */
+ if (memcmp((uint8_t *)msg + pad_len, hash, msg_len - pad_len)) {
+ debug("In RSAVerify(): Hash check failed!\n");
+ return -EACCES;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT
+static void u32_i2osp(uint32_t val, uint8_t *buf)
+{
+ buf[0] = (uint8_t)((val >> 24) & 0xff);
+ buf[1] = (uint8_t)((val >> 16) & 0xff);
+ buf[2] = (uint8_t)((val >> 8) & 0xff);
+ buf[3] = (uint8_t)((val >> 0) & 0xff);
+}
+
+/**
+ * mask_generation_function1() - generate an octet string
+ *
+ * Generate an octet string used to check rsa signature.
+ * It use an input octet string and a hash function.
+ *
+ * @checksum: A Hash function
+ * @seed: Specifies an input variable octet string
+ * @seed_len: Size of the input octet string
+ * @output: Specifies the output octet string
+ * @output_len: Size of the output octet string
+ * @return 0 if the octet string was correctly generated, others on error
+ */
+static int mask_generation_function1(struct checksum_algo *checksum,
+ uint8_t *seed, int seed_len,
+ uint8_t *output, int output_len)
+{
+ struct image_region region[2];
+ int ret = 0, i, i_output = 0, region_count = 2;
+ uint32_t counter = 0;
+ uint8_t buf_counter[4], *tmp;
+ int hash_len = checksum->checksum_len;
+
+ memset(output, 0, output_len);
+
+ region[0].data = seed;
+ region[0].size = seed_len;
+ region[1].data = &buf_counter[0];
+ region[1].size = 4;
+
+ tmp = malloc(hash_len);
+ if (!tmp) {
+ debug("%s: can't allocate array tmp\n", __func__);
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ while (i_output < output_len) {
+ u32_i2osp(counter, &buf_counter[0]);
+
+ ret = checksum->calculate(checksum->name,
+ region, region_count,
+ tmp);
+ if (ret < 0) {
+ debug("%s: Error in checksum calculation\n", __func__);
+ goto out;
+ }
+
+ i = 0;
+ while ((i_output < output_len) && (i < hash_len)) {
+ output[i_output] = tmp[i];
+ i_output++;
+ i++;
+ }
+
+ counter++;
+ }
+
+out:
+ free(tmp);
+
+ return ret;
+}
+
+static int compute_hash_prime(struct checksum_algo *checksum,
+ uint8_t *pad, int pad_len,
+ uint8_t *hash, int hash_len,
+ uint8_t *salt, int salt_len,
+ uint8_t *hprime)
+{
+ struct image_region region[3];
+ int ret, region_count = 3;
+
+ region[0].data = pad;
+ region[0].size = pad_len;
+ region[1].data = hash;
+ region[1].size = hash_len;
+ region[2].data = salt;
+ region[2].size = salt_len;
+
+ ret = checksum->calculate(checksum->name, region, region_count, hprime);
+ if (ret < 0) {
+ debug("%s: Error in checksum calculation\n", __func__);
+ goto out;
+ }
+
+out:
+ return ret;
+}
+
+int padding_pss_verify(struct image_sign_info *info,
+ uint8_t *msg, int msg_len,
+ const uint8_t *hash, int hash_len)
+{
+ uint8_t *masked_db = NULL;
+ int masked_db_len = msg_len - hash_len - 1;
+ uint8_t *h = NULL, *hprime = NULL;
+ int h_len = hash_len;
+ uint8_t *db_mask = NULL;
+ int db_mask_len = masked_db_len;
+ uint8_t *db = NULL, *salt = NULL;
+ int db_len = masked_db_len, salt_len = msg_len - hash_len - 2;
+ uint8_t pad_zero[8] = { 0 };
+ int ret, i, leftmost_bits = 1;
+ uint8_t leftmost_mask;
+ struct checksum_algo *checksum = info->checksum;
+
+ /* first, allocate everything */
+ masked_db = malloc(masked_db_len);
+ h = malloc(h_len);
+ db_mask = malloc(db_mask_len);
+ db = malloc(db_len);
+ salt = malloc(salt_len);
+ hprime = malloc(hash_len);
+ if (!masked_db || !h || !db_mask || !db || !salt || !hprime) {
+ printf("%s: can't allocate some buffer\n", __func__);
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ /* step 4: check if the last byte is 0xbc */
+ if (msg[msg_len - 1] != 0xbc) {
+ printf("%s: invalid pss padding (0xbc is missing)\n", __func__);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ /* step 5 */
+ memcpy(masked_db, msg, masked_db_len);
+ memcpy(h, msg + masked_db_len, h_len);
+
+ /* step 6 */
+ leftmost_mask = (0xff >> (8 - leftmost_bits)) << (8 - leftmost_bits);
+ if (masked_db[0] & leftmost_mask) {
+ printf("%s: invalid pss padding ", __func__);
+ printf("(leftmost bit of maskedDB not zero)\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ /* step 7 */
+ mask_generation_function1(checksum, h, h_len, db_mask, db_mask_len);
+
+ /* step 8 */
+ for (i = 0; i < db_len; i++)
+ db[i] = masked_db[i] ^ db_mask[i];
+
+ /* step 9 */
+ db[0] &= 0xff >> leftmost_bits;
+
+ /* step 10 */
+ if (db[0] != 0x01) {
+ printf("%s: invalid pss padding ", __func__);
+ printf("(leftmost byte of db isn't 0x01)\n");
+ ret = EINVAL;
+ goto out;
+ }
+
+ /* step 11 */
+ memcpy(salt, &db[1], salt_len);
+
+ /* step 12 & 13 */
+ compute_hash_prime(checksum, pad_zero, 8,
+ (uint8_t *)hash, hash_len,
+ salt, salt_len, hprime);
+
+ /* step 14 */
+ ret = memcmp(h, hprime, hash_len);
+
+out:
+ free(hprime);
+ free(salt);
+ free(db);
+ free(db_mask);
+ free(h);
+ free(masked_db);
+
+ return ret;
+}
+#endif
+
/**
* rsa_verify_key() - Verify a signature against some data using RSA Key
*
* Verify a RSA PKCS1.5 signature against an expected hash using
* the RSA Key properties in prop structure.
*
+ * @info: Specifies key and FIT information
* @prop: Specifies key
* @sig: Signature
* @sig_len: Number of bytes in signature
* @hash: Pointer to the expected hash
* @key_len: Number of bytes in rsa key
- * @algo: Checksum algo structure having information on DER encoding etc.
* @return 0 if verified, -ve on error
*/
-static int rsa_verify_key(struct key_prop *prop, const uint8_t *sig,
+static int rsa_verify_key(struct image_sign_info *info,
+ struct key_prop *prop, const uint8_t *sig,
const uint32_t sig_len, const uint8_t *hash,
- const uint32_t key_len, struct checksum_algo *algo)
+ const uint32_t key_len)
{
- int pad_len;
int ret;
#if !defined(USE_HOSTCC)
struct udevice *mod_exp_dev;
#endif
+ struct checksum_algo *checksum = info->checksum;
+ struct padding_algo *padding = info->padding;
+ int hash_len = checksum->checksum_len;
- if (!prop || !sig || !hash || !algo)
+ if (!prop || !sig || !hash || !checksum)
return -EIO;
if (sig_len != (prop->num_bits / 8)) {
return -EINVAL;
}
- debug("Checksum algorithm: %s", algo->name);
+ debug("Checksum algorithm: %s", checksum->name);
/* Sanity check for stack size */
if (sig_len > RSA_MAX_SIG_BITS / 8) {
return ret;
}
- pad_len = key_len - algo->checksum_len;
-
- /* Check pkcs1.5 padding bytes. */
- ret = rsa_verify_padding(buf, pad_len, algo);
+ ret = padding->verify(info, buf, key_len, hash, hash_len);
if (ret) {
- debug("In RSAVerify(): Padding check failed!\n");
- return -EINVAL;
- }
-
- /* Check hash. */
- if (memcmp((uint8_t *)buf + pad_len, hash, sig_len - pad_len)) {
- debug("In RSAVerify(): Hash check failed!\n");
- return -EACCES;
+ debug("In RSAVerify(): padding check failed!\n");
+ return ret;
}
return 0;
return -EFAULT;
}
- ret = rsa_verify_key(&prop, sig, sig_len, hash,
- info->crypto->key_len, info->checksum);
+ ret = rsa_verify_key(info, &prop, sig, sig_len, hash,
+ info->crypto->key_len);
return ret;
}
CONFIG_RTC_FTRTC010
CONFIG_RTC_IMXDI
CONFIG_RTC_M41T11
-CONFIG_RTC_M41T62
CONFIG_RTC_MC13XXX
CONFIG_RTC_MCFRRTC
CONFIG_RTC_MCP79411
handle.write(struct.pack(">I", size))
return struct.unpack(">I", total_size)[0]
- def test_with_algo(sha_algo):
+ def test_with_algo(sha_algo, padding):
"""Test verified boot with the given hash algorithm.
This is the main part of the test code. The same procedure is followed
# Build the FIT, but don't sign anything yet
cons.log.action('%s: Test FIT with signed images' % sha_algo)
- make_fit('sign-images-%s.its' % sha_algo)
+ make_fit('sign-images-%s%s.its' % (sha_algo , padding))
run_bootm(sha_algo, 'unsigned images', 'dev-', True)
# Sign images with our dev keys
dtc('sandbox-u-boot.dts')
cons.log.action('%s: Test FIT with signed configuration' % sha_algo)
- make_fit('sign-configs-%s.its' % sha_algo)
+ make_fit('sign-configs-%s%s.its' % (sha_algo , padding))
run_bootm(sha_algo, 'unsigned config', '%s+ OK' % sha_algo, True)
# Sign images with our dev keys
fit_check_sign = cons.config.build_dir + '/tools/fit_check_sign'
dtc_args = '-I dts -O dtb -i %s' % tmpdir
dtb = '%ssandbox-u-boot.dtb' % tmpdir
- sig_node = '/configurations/conf@1/signature@1'
+ sig_node = '/configurations/conf-1/signature'
# Create an RSA key pair
public_exponent = 65537
# afterwards.
old_dtb = cons.config.dtb
cons.config.dtb = dtb
- test_with_algo('sha1')
- test_with_algo('sha256')
+ test_with_algo('sha1','')
+ test_with_algo('sha1','-pss')
+ test_with_algo('sha256','')
+ test_with_algo('sha256','-pss')
finally:
# Go back to the original U-Boot with the correct dtb.
cons.config.dtb = old_dtb
--- /dev/null
+/dts-v1/;
+
+/ {
+ description = "Chrome OS kernel image with one or more FDT blobs";
+ #address-cells = <1>;
+
+ images {
+ kernel {
+ data = /incbin/("test-kernel.bin");
+ type = "kernel_noload";
+ arch = "sandbox";
+ os = "linux";
+ compression = "none";
+ load = <0x4>;
+ entry = <0x8>;
+ kernel-version = <1>;
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+ fdt-1 {
+ description = "snow";
+ data = /incbin/("sandbox-kernel.dtb");
+ type = "flat_dt";
+ arch = "sandbox";
+ compression = "none";
+ fdt-version = <1>;
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+ };
+ configurations {
+ default = "conf-1";
+ conf-1 {
+ kernel = "kernel";
+ fdt = "fdt-1";
+ signature {
+ algo = "sha1,rsa2048";
+ padding = "pss";
+ key-name-hint = "dev";
+ sign-images = "fdt", "kernel";
+ };
+ };
+ };
+};
#address-cells = <1>;
images {
- kernel@1 {
+ kernel {
data = /incbin/("test-kernel.bin");
type = "kernel_noload";
arch = "sandbox";
load = <0x4>;
entry = <0x8>;
kernel-version = <1>;
- hash@1 {
+ hash-1 {
algo = "sha1";
};
};
- fdt@1 {
+ fdt-1 {
description = "snow";
data = /incbin/("sandbox-kernel.dtb");
type = "flat_dt";
arch = "sandbox";
compression = "none";
fdt-version = <1>;
- hash@1 {
+ hash-1 {
algo = "sha1";
};
};
};
configurations {
- default = "conf@1";
- conf@1 {
- kernel = "kernel@1";
- fdt = "fdt@1";
- signature@1 {
+ default = "conf-1";
+ conf-1 {
+ kernel = "kernel";
+ fdt = "fdt-1";
+ signature {
algo = "sha1,rsa2048";
key-name-hint = "dev";
sign-images = "fdt", "kernel";
--- /dev/null
+/dts-v1/;
+
+/ {
+ description = "Chrome OS kernel image with one or more FDT blobs";
+ #address-cells = <1>;
+
+ images {
+ kernel {
+ data = /incbin/("test-kernel.bin");
+ type = "kernel_noload";
+ arch = "sandbox";
+ os = "linux";
+ compression = "none";
+ load = <0x4>;
+ entry = <0x8>;
+ kernel-version = <1>;
+ hash-1 {
+ algo = "sha256";
+ };
+ };
+ fdt-1 {
+ description = "snow";
+ data = /incbin/("sandbox-kernel.dtb");
+ type = "flat_dt";
+ arch = "sandbox";
+ compression = "none";
+ fdt-version = <1>;
+ hash-1 {
+ algo = "sha256";
+ };
+ };
+ };
+ configurations {
+ default = "conf-1";
+ conf-1 {
+ kernel = "kernel";
+ fdt = "fdt-1";
+ signature {
+ algo = "sha256,rsa2048";
+ padding = "pss";
+ key-name-hint = "dev";
+ sign-images = "fdt", "kernel";
+ };
+ };
+ };
+};
#address-cells = <1>;
images {
- kernel@1 {
+ kernel {
data = /incbin/("test-kernel.bin");
type = "kernel_noload";
arch = "sandbox";
load = <0x4>;
entry = <0x8>;
kernel-version = <1>;
- hash@1 {
+ hash-1 {
algo = "sha256";
};
};
- fdt@1 {
+ fdt-1 {
description = "snow";
data = /incbin/("sandbox-kernel.dtb");
type = "flat_dt";
arch = "sandbox";
compression = "none";
fdt-version = <1>;
- hash@1 {
+ hash-1 {
algo = "sha256";
};
};
};
configurations {
- default = "conf@1";
- conf@1 {
- kernel = "kernel@1";
- fdt = "fdt@1";
- signature@1 {
+ default = "conf-1";
+ conf-1 {
+ kernel = "kernel";
+ fdt = "fdt-1";
+ signature {
algo = "sha256,rsa2048";
key-name-hint = "dev";
sign-images = "fdt", "kernel";
--- /dev/null
+/dts-v1/;
+
+/ {
+ description = "Chrome OS kernel image with one or more FDT blobs";
+ #address-cells = <1>;
+
+ images {
+ kernel {
+ data = /incbin/("test-kernel.bin");
+ type = "kernel_noload";
+ arch = "sandbox";
+ os = "linux";
+ compression = "none";
+ load = <0x4>;
+ entry = <0x8>;
+ kernel-version = <1>;
+ signature {
+ algo = "sha1,rsa2048";
+ padding = "pss";
+ key-name-hint = "dev";
+ };
+ };
+ fdt-1 {
+ description = "snow";
+ data = /incbin/("sandbox-kernel.dtb");
+ type = "flat_dt";
+ arch = "sandbox";
+ compression = "none";
+ fdt-version = <1>;
+ signature {
+ algo = "sha1,rsa2048";
+ padding = "pss";
+ key-name-hint = "dev";
+ };
+ };
+ };
+ configurations {
+ default = "conf-1";
+ conf-1 {
+ kernel = "kernel";
+ fdt = "fdt-1";
+ };
+ };
+};
#address-cells = <1>;
images {
- kernel@1 {
+ kernel {
data = /incbin/("test-kernel.bin");
type = "kernel_noload";
arch = "sandbox";
load = <0x4>;
entry = <0x8>;
kernel-version = <1>;
- signature@1 {
+ signature {
algo = "sha1,rsa2048";
key-name-hint = "dev";
};
};
- fdt@1 {
+ fdt-1 {
description = "snow";
data = /incbin/("sandbox-kernel.dtb");
type = "flat_dt";
arch = "sandbox";
compression = "none";
fdt-version = <1>;
- signature@1 {
+ signature {
algo = "sha1,rsa2048";
key-name-hint = "dev";
};
};
};
configurations {
- default = "conf@1";
- conf@1 {
- kernel = "kernel@1";
- fdt = "fdt@1";
+ default = "conf-1";
+ conf-1 {
+ kernel = "kernel";
+ fdt = "fdt-1";
};
};
};
--- /dev/null
+/dts-v1/;
+
+/ {
+ description = "Chrome OS kernel image with one or more FDT blobs";
+ #address-cells = <1>;
+
+ images {
+ kernel {
+ data = /incbin/("test-kernel.bin");
+ type = "kernel_noload";
+ arch = "sandbox";
+ os = "linux";
+ compression = "none";
+ load = <0x4>;
+ entry = <0x8>;
+ kernel-version = <1>;
+ signature {
+ algo = "sha256,rsa2048";
+ padding = "pss";
+ key-name-hint = "dev";
+ };
+ };
+ fdt-1 {
+ description = "snow";
+ data = /incbin/("sandbox-kernel.dtb");
+ type = "flat_dt";
+ arch = "sandbox";
+ compression = "none";
+ fdt-version = <1>;
+ signature {
+ algo = "sha256,rsa2048";
+ padding = "pss";
+ key-name-hint = "dev";
+ };
+ };
+ };
+ configurations {
+ default = "conf-1";
+ conf-1 {
+ kernel = "kernel";
+ fdt = "fdt-1";
+ };
+ };
+};
#address-cells = <1>;
images {
- kernel@1 {
+ kernel {
data = /incbin/("test-kernel.bin");
type = "kernel_noload";
arch = "sandbox";
load = <0x4>;
entry = <0x8>;
kernel-version = <1>;
- signature@1 {
+ signature {
algo = "sha256,rsa2048";
key-name-hint = "dev";
};
};
- fdt@1 {
+ fdt-1 {
description = "snow";
data = /incbin/("sandbox-kernel.dtb");
type = "flat_dt";
arch = "sandbox";
compression = "none";
fdt-version = <1>;
- signature@1 {
+ signature {
algo = "sha256,rsa2048";
key-name-hint = "dev";
};
};
};
configurations {
- default = "conf@1";
- conf@1 {
- kernel = "kernel@1";
- fdt = "fdt@1";
+ default = "conf-1";
+ conf-1 {
+ kernel = "kernel";
+ fdt = "fdt-1";
};
};
};
{
const char *node_name;
char *algo_name;
+ const char *padding_name;
node_name = fit_get_name(fit, noffset, NULL);
if (fit_image_hash_get_algo(fit, noffset, &algo_name)) {
return -1;
}
+ padding_name = fdt_getprop(fit, noffset, "padding", NULL);
+
memset(info, '\0', sizeof(*info));
info->keydir = keydir;
info->keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL);
info->name = strdup(algo_name);
info->checksum = image_get_checksum_algo(algo_name);
info->crypto = image_get_crypto_algo(algo_name);
+ info->padding = image_get_padding_algo(padding_name);
info->require_keys = require_keys;
info->engine_id = engine_id;
if (!info->checksum || !info->crypto) {
projects / oweals / u-boot.git / commitdiff