mpc83xx: add ids8313 support
authorHeiko Schocher <hs@denx.de>
Sat, 25 Jan 2014 06:53:48 +0000 (07:53 +0100)
committerKim Phillips <kim.phillips@linaro.org>
Thu, 24 Apr 2014 00:07:54 +0000 (19:07 -0500)
add support for the ids8313 board.

CPU:   e300c3, MPC8313, Rev: 2.1 at 396 MHz, CSB: 132 MHz
I2C:   ready
SPI:   ready
DRAM:  128 MiB (DDR2, 32-bit, ECC off, 264 MHz)
Flash: 8 MiB
NAND:  128 MiB
Net:   TSEC0, TSEC1 [PRIME]

public key on NOR flash start

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
board/ids/ids8313/Makefile [new file with mode: 0644]
board/ids/ids8313/ids8313.c [new file with mode: 0644]
boards.cfg
include/configs/ids8313.h [new file with mode: 0644]

diff --git a/board/ids/ids8313/Makefile b/board/ids/ids8313/Makefile
new file mode 100644 (file)
index 0000000..56cfd40
--- /dev/null
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2013
+# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  = ids8313.o
diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c
new file mode 100644 (file)
index 0000000..f742143
--- /dev/null
@@ -0,0 +1,208 @@
+/*
+ * (C) Copyright 2013
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (c) 2011 IDS GmbH, Germany
+ * ids8313.c - ids8313 board support.
+ *
+ * Sergej Stepanov <ste@ids.de>
+ * Based on board/freescale/mpc8313erdb/mpc8313erdb.c
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <spi.h>
+#include <libfdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+/** CPLD contains the info about:
+ * - board type: *pCpld & 0xF0
+ * - hw-revision: *pCpld & 0x0F
+ * - cpld-revision: *pCpld+1
+ */
+int checkboard(void)
+{
+       char *pcpld = (char *)CONFIG_SYS_CPLD_BASE;
+       u8 u8Vers = readb(pcpld);
+       u8 u8Revs = readb(pcpld + 1);
+
+       printf("Board: ");
+       switch (u8Vers & 0xF0) {
+       case '\x40':
+               printf("CU73X");
+               break;
+       case '\x50':
+               printf("CC73X");
+               break;
+       default:
+               printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs);
+               return 0;
+       }
+       printf("\nInfo:  HW-Rev: %i, CPLD-Rev: %i\n",
+              u8Vers & 0x0F, u8Revs & 0xFF);
+       return 0;
+}
+
+/*
+ *  fixed sdram init
+ */
+int fixed_sdram(unsigned long config)
+{
+       immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+       u32 msize = CONFIG_SYS_DDR_SIZE << 20;
+
+#ifndef CONFIG_SYS_RAMBOOT
+       u32 msize_log2 = __ilog2(msize);
+
+       out_be32(&im->sysconf.ddrlaw[0].bar,
+                (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
+       out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+       out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+       sync();
+
+       /*
+        * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+        * or the DDR2 controller may fail to initialize correctly.
+        */
+       udelay(50000);
+
+       out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+       out_be32(&im->ddr.cs_config[0], config);
+
+       /* currently we use only one CS, so disable the other banks */
+       out_be32(&im->ddr.cs_config[1], 0);
+       out_be32(&im->ddr.cs_config[2], 0);
+       out_be32(&im->ddr.cs_config[3], 0);
+
+       out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+       out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+       out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+       out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+       out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
+       out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
+
+       out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+       out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
+
+       out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+       out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
+       sync();
+       udelay(300);
+
+       /* enable DDR controller */
+       setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+       /* now check the real size */
+       disable_addr_trans();
+       msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
+       enable_addr_trans();
+#endif
+       return msize;
+}
+
+static int setup_sdram(void)
+{
+       u32 msize = CONFIG_SYS_DDR_SIZE << 20;
+       long int size_01, size_02;
+
+       size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
+       size_02 = fixed_sdram(CONFIG_SYS_DDR_CONFIG_256);
+
+       if (size_01 > size_02)
+               msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
+       else
+               msize = size_02;
+
+       return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+       immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+       fsl_lbc_t *lbc = &im->im_lbc;
+       u32 msize = 0;
+
+       if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+               return -1;
+
+       msize = setup_sdram();
+
+       out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+       out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+       sync();
+
+       return msize;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+       ft_cpu_setup(blob, bd);
+}
+#endif
+
+/* gpio mask for spi_cs */
+#define IDSCPLD_SPI_CS_MASK            0x00000001
+/* spi_cs multiplexed through cpld */
+#define IDSCPLD_SPI_CS_BASE            (CONFIG_SYS_CPLD_BASE + 0xf)
+
+#if defined(CONFIG_MISC_INIT_R)
+/* srp umcr mask for rts */
+#define IDSUMCR_RTS_MASK 0x04
+int misc_init_r(void)
+{
+       /*srp*/
+       duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0];
+       duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1];
+
+       gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+       u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
+
+       /* deactivate spi_cs channels */
+       out_8(spi_base, 0);
+       /* deactivate the spi_cs */
+       setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK);
+       /*srp - deactivate rts*/
+       out_8(&uart1->umcr, IDSUMCR_RTS_MASK);
+       out_8(&uart2->umcr, IDSUMCR_RTS_MASK);
+
+
+       gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE;
+       return 0;
+}
+#endif
+
+#ifdef CONFIG_MPC8XXX_SPI
+/*
+ * The following are used to control the SPI chip selects
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+       return bus == 0 && ((cs >= 0) && (cs <= 2));
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+       gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+       u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
+
+       /* select the spi_cs channel */
+       out_8(spi_base, 1 << slave->cs);
+       /* activate the spi_cs */
+       clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+       gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+       u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
+
+       /* select the spi_cs channel */
+       out_8(spi_base, 1 << slave->cs);
+       /* deactivate the spi_cs */
+       setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
+}
+#endif /* CONFIG_HARD_SPI */
index c8270b2de06e1ae7544c9f3c555cf0ad7549e4bb..83fc3afdbf605742b1170f2c99dd6fec9aa0a8a5 100644 (file)
@@ -719,6 +719,7 @@ Active  powerpc     mpc83xx        -           freescale       mpc8360emds
 Active  powerpc     mpc83xx        -           freescale       mpc837xemds         MPC837XEMDS                          -                                                                                                                                 Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc837xemds         MPC837XEMDS_HOST                     MPC837XEMDS:PCI                                                                                                                   Dave Liu <daveliu@freescale.com>
 Active  powerpc     mpc83xx        -           freescale       mpc837xerdb         MPC837XERDB                          -                                                                                                                                 Joe D'Abbraccio <ljd015@freescale.com>
+Active  powerpc     mpc83xx        -           ids             ids8313             ids8313                              ids8313:SYS_TEXT_BASE=0xFFF00000                                                                                                  Heiko Schocher <hs@denx.de>
 Active  powerpc     mpc83xx        -           keymile         km83xx              kmcoge5ne                            km8360:KMCOGE5NE                                                                                                                  Holger Brunck <holger.brunck@keymile.com>
 Active  powerpc     mpc83xx        -           keymile         km83xx              kmeter1                              km8360:KMETER1                                                                                                                    Holger Brunck <holger.brunck@keymile.com>
 Active  powerpc     mpc83xx        -           keymile         km83xx              kmopti2                              tuxx1:KMOPTI2                                                                                                                     Holger Brunck <holger.brunck@keymile.com>
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
new file mode 100644 (file)
index 0000000..613f7e1
--- /dev/null
@@ -0,0 +1,587 @@
+/*
+ * (C) Copyright 2013
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (c) 2011 IDS GmbH, Germany
+ * Sergej Stepanov <ste@ids.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MPC831x
+#define CONFIG_MPC8313
+#define CONFIG_IDS8313
+
+#define CONFIG_FSL_ELBC
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT \
+       "\nEnter password - autoboot in %d seconds...\n", CONFIG_BOOTDELAY
+#define CONFIG_AUTOBOOT_DELAY_STR      "ids"
+#define CONFIG_BOOT_RETRY_TIME         900
+#define CONFIG_BOOT_RETRY_MIN          30
+#define CONFIG_BOOTDELAY               1
+#define CONFIG_RESET_TO_RETRY
+
+#define CONFIG_83XX_CLKIN              66000000        /* in Hz */
+#define CONFIG_SYS_CLK_FREQ            CONFIG_83XX_CLKIN
+
+#define CONFIG_SYS_IMMR                0xF0000000
+
+#define CONFIG_SYS_ACR_PIPE_DEP        3       /* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT          3       /* Arbiter repeat count (0-7) */
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66.000MHz, then
+ * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
+ */
+#define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
+                            HRCWL_DDR_TO_SCB_CLK_2X1 |\
+                            HRCWL_CSB_TO_CLKIN_2X1 |\
+                            HRCWL_CORE_TO_CSB_2X1)
+
+#define CONFIG_SYS_HRCW_HIGH   (HRCWH_PCI_HOST |\
+                                HRCWH_CORE_ENABLE |\
+                                HRCWH_FROM_0XFFF00100 |\
+                                HRCWH_BOOTSEQ_DISABLE |\
+                                HRCWH_SW_WATCHDOG_DISABLE |\
+                                HRCWH_ROM_LOC_LOCAL_8BIT |\
+                                HRCWH_RL_EXT_LEGACY |\
+                                HRCWH_TSEC1M_IN_MII |\
+                                HRCWH_TSEC2M_IN_MII |\
+                                HRCWH_BIG_ENDIAN)
+
+#define CONFIG_SYS_SICRH       0x00000000
+#define CONFIG_SYS_SICRL       (SICRL_LBC | SICRL_SPI_D)
+
+#define CONFIG_HWCONFIG
+
+#define CONFIG_SYS_HID0_INIT   0x000000000
+#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK |\
+                                HID0_ENABLE_INSTRUCTION_CACHE |\
+                                HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
+
+#define CONFIG_SYS_HID2        (HID2_HBE | 0x00020000)
+
+/*
+ * Definitions for initial stack pointer and data area (in DCACHE )
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR       0xFD000000
+#define CONFIG_SYS_INIT_RAM_SIZE       0x1000  /* End of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_SIZE       0x100
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE \
+                                        - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Local Bus LCRR and LBCR regs
+ */
+#define CONFIG_SYS_LCRR_EADC           LCRR_EADC_1
+#define CONFIG_SYS_LCRR_CLKDIV         LCRR_CLKDIV_2
+#define CONFIG_SYS_LBC_LBCR            (0x00040000 |\
+                                        (0xFF << LBCR_BMT_SHIFT) |\
+                                        0xF)
+
+#define CONFIG_SYS_LBC_MRTPR           0x20000000
+
+/*
+ * Internal Definitions
+ */
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE            0x00000000
+#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+
+/*
+ * Manually set up DDR parameters,
+ * as this board has not the SPD connected to I2C.
+ */
+#define CONFIG_SYS_DDR_SIZE            256             /* MB */
+#define CONFIG_SYS_DDR_CONFIG          (CSCONFIG_EN |\
+                                        0x00010000 |\
+                                        CSCONFIG_ROW_BIT_13 |\
+                                        CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_CONFIG_256      (CONFIG_SYS_DDR_CONFIG | \
+                                        CSCONFIG_BANK_BIT_3)
+
+#define CONFIG_SYS_DDR_TIMING_3        (1 << 16)       /* ext refrec */
+#define CONFIG_SYS_DDR_TIMING_0        ((3 << TIMING_CFG0_RWT_SHIFT) |\
+                               (3 << TIMING_CFG0_WRT_SHIFT) |\
+                               (3 << TIMING_CFG0_RRT_SHIFT) |\
+                               (3 << TIMING_CFG0_WWT_SHIFT) |\
+                               (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
+                               (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
+                               (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+                               (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+#define CONFIG_SYS_DDR_TIMING_1        ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
+                               (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
+                               (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
+                               (7 << TIMING_CFG1_CASLAT_SHIFT) |\
+                               (4 << TIMING_CFG1_REFREC_SHIFT) |\
+                               (4 << TIMING_CFG1_WRREC_SHIFT) |\
+                               (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
+                               (2 << TIMING_CFG1_WRTORD_SHIFT))
+#define CONFIG_SYS_DDR_TIMING_2        ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
+                               (5 << TIMING_CFG2_CPO_SHIFT) |\
+                               (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
+                               (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
+                               (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
+                               (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
+                               (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
+
+#define CONFIG_SYS_DDR_INTERVAL        ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
+                               (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+
+#define CONFIG_SYS_SDRAM_CFG           (SDRAM_CFG_SREN |\
+                                        SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
+                                        SDRAM_CFG_DBW_32 |\
+                                        SDRAM_CFG_SDRAM_TYPE_DDR2)
+
+#define CONFIG_SYS_SDRAM_CFG2          0x00401000
+#define CONFIG_SYS_DDR_MODE            ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
+                                        (0x0242 << SDRAM_MODE_SD_SHIFT))
+#define CONFIG_SYS_DDR_MODE_2          0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
+#define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_EN |\
+                                        DDRCDR_PZ_NOMZ |\
+                                        DDRCDR_NZ_NOMZ |\
+                                        DDRCDR_ODT |\
+                                        DDRCDR_M_ODR |\
+                                        DDRCDR_Q_DRN)
+
+/*
+ * on-board devices
+ */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC2
+#define CONFIG_TSEC_ENET
+#define CONFIG_NET_MULTI
+#define CONFIG_HARD_SPI
+#define CONFIG_HARD_I2C
+
+/*
+ * NOR FLASH setup
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_WIDTH     FLASH_CFI_8BIT
+#define CONFIG_FLASH_SHOW_PROGRESS     50
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#define CONFIG_SYS_FLASH_BASE          0xFF800000
+#define CONFIG_SYS_FLASH_SIZE          8
+#define CONFIG_SYS_FLASH_PROTECTION
+
+#define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM     0x80000016
+
+#define CONFIG_SYS_BR0_PRELIM          (CONFIG_SYS_FLASH_BASE |\
+                                        BR_PS_8 |\
+                                        BR_MS_GPCM |\
+                                        BR_V)
+
+#define CONFIG_SYS_OR0_PRELIM          (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
+                                        OR_GPCM_SCY_10 |\
+                                        OR_GPCM_EHTR |\
+                                        OR_GPCM_TRLX |\
+                                        OR_GPCM_CSNT |\
+                                        OR_GPCM_EAD)
+#define CONFIG_SYS_MAX_FLASH_BANKS     1
+#define CONFIG_SYS_MAX_FLASH_SECT      128
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT    60000
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500
+
+/*
+ * NAND FLASH setup
+ */
+#define CONFIG_SYS_NAND_BASE           0xE1000000
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_MAX_CHIPS      1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_PAGE_SIZE      (2048)
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 << 10)
+#define NAND_CACHE_PAGES               64
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM    CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM     0x8000000E
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
+
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_NAND_BASE) |\
+                                (2<<BR_DECC_SHIFT) |\
+                                BR_PS_8 |\
+                                BR_MS_FCM |\
+                                BR_V)
+
+#define CONFIG_SYS_OR1_PRELIM  (0xFFFF8000 |\
+                                OR_FCM_PGS |\
+                                OR_FCM_CSCT |\
+                                OR_FCM_CST |\
+                                OR_FCM_CHT |\
+                                OR_FCM_SCY_4 |\
+                                OR_FCM_TRLX |\
+                                OR_FCM_EHTR |\
+                                OR_FCM_RST)
+
+/*
+ * MRAM setup
+ */
+#define CONFIG_SYS_MRAM_BASE           0xE2000000
+#define CONFIG_SYS_MRAM_SIZE           0x20000 /* 128 Kb */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM    CONFIG_SYS_MRAM_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM     0x80000010      /* 128 Kb  */
+
+#define CONFIG_SYS_OR_TIMING_MRAM
+
+#define CONFIG_SYS_BR2_PRELIM          (CONFIG_SYS_MRAM_BASE |\
+                                        BR_PS_8 |\
+                                        BR_MS_GPCM |\
+                                        BR_V)
+
+#define CONFIG_SYS_OR2_PRELIM          0xFFFE0C74
+
+/*
+ * CPLD setup
+ */
+#define CONFIG_SYS_CPLD_BASE           0xE3000000
+#define CONFIG_SYS_CPLD_SIZE           0x8000
+#define CONFIG_SYS_LBLAWBAR3_PRELIM    CONFIG_SYS_CPLD_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM     0x8000000E
+
+#define CONFIG_SYS_OR_TIMING_MRAM
+
+#define CONFIG_SYS_BR3_PRELIM          (CONFIG_SYS_CPLD_BASE |\
+                                        BR_PS_8 |\
+                                        BR_MS_GPCM |\
+                                        BR_V)
+
+#define CONFIG_SYS_OR3_PRELIM          0xFFFF8814
+
+/*
+ * HW-Watchdog
+ */
+#define CONFIG_WATCHDOG                1
+#define CONFIG_SYS_WATCHDOG_VALUE      0xFFFF
+
+/*
+ * I2C setup
+ */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED       400000
+#define CONFIG_SYS_FSL_I2C_SLAVE       0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET      0x3100
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR        0x51
+
+/*
+ * SPI setup
+ */
+#ifdef CONFIG_HARD_SPI
+#define CONFIG_MPC8XXX_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_SYS_GPIO1_PRELIM
+#define CONFIG_SYS_GPIO1_DIR           0x00000001
+#define CONFIG_SYS_GPIO1_DAT           0x00000001
+#endif
+
+/*
+ * Ethernet setup
+ */
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME              "TSEC0"
+#define CONFIG_SYS_TSEC1_OFFSET        0x24000
+#define TSEC1_PHY_ADDR                 0x1
+#define TSEC1_FLAGS                    TSEC_GIGABIT
+#define TSEC1_PHYIDX                   0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME              "TSEC1"
+#define CONFIG_SYS_TSEC2_OFFSET        0x25000
+#define TSEC2_PHY_ADDR                 0x3
+#define TSEC2_FLAGS                    TSEC_GIGABIT
+#define TSEC2_PHYIDX                   0
+#endif
+#define CONFIG_ETHPRIME                "TSEC1"
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX              1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+
+#define CONFIG_SYS_BAUDRATE_TABLE      \
+       {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR + 0x4600)
+#define CONFIG_SYS_NS16550_CLK         (CONFIG_83XX_CLKIN * 2)
+
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_SYS_SCCR_USBDRCM        3
+
+/*
+ * BAT's
+ */
+#define CONFIG_HIGH_BATS
+
+/* DDR @ 0x00000000 */
+#define CONFIG_SYS_IBAT0L              (CONFIG_SYS_SDRAM_BASE |\
+                                        BATL_PP_10)
+#define CONFIG_SYS_IBAT0U              (CONFIG_SYS_SDRAM_BASE |\
+                                        BATU_BL_256M |\
+                                        BATU_VS |\
+                                        BATU_VP)
+#define CONFIG_SYS_DBAT0L              CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U              CONFIG_SYS_IBAT0U
+
+/* Initial RAM @ 0xFD000000 */
+#define CONFIG_SYS_IBAT1L              (CONFIG_SYS_INIT_RAM_ADDR |\
+                                        BATL_PP_10 |\
+                                        BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U              (CONFIG_SYS_INIT_RAM_ADDR |\
+                                        BATU_BL_256K |\
+                                        BATU_VS |\
+                                        BATU_VP)
+#define CONFIG_SYS_DBAT1L              CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U              CONFIG_SYS_IBAT1U
+
+/* FLASH @ 0xFF800000 */
+#define CONFIG_SYS_IBAT2L              (CONFIG_SYS_FLASH_BASE |\
+                                        BATL_PP_10 |\
+                                        BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U              (CONFIG_SYS_FLASH_BASE |\
+                                        BATU_BL_8M |\
+                                        BATU_VS |\
+                                        BATU_VP)
+#define CONFIG_SYS_DBAT2L              (CONFIG_SYS_FLASH_BASE |\
+                                        BATL_PP_10 |\
+                                        BATL_CACHEINHIBIT |\
+                                        BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U              CONFIG_SYS_IBAT2U
+
+#define CONFIG_SYS_IBAT3L              (0)
+#define CONFIG_SYS_IBAT3U              (0)
+#define CONFIG_SYS_DBAT3L              CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U              CONFIG_SYS_IBAT3U
+
+#define CONFIG_SYS_IBAT4L              (0)
+#define CONFIG_SYS_IBAT4U              (0)
+#define CONFIG_SYS_DBAT4L              CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U              CONFIG_SYS_IBAT4U
+
+/* IMMRBAR @ 0xF0000000 */
+#define CONFIG_SYS_IBAT5L              (CONFIG_SYS_IMMR |\
+                                        BATL_PP_10 |\
+                                        BATL_CACHEINHIBIT |\
+                                        BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U              (CONFIG_SYS_IMMR |\
+                                        BATU_BL_128M |\
+                                        BATU_VS |\
+                                        BATU_VP)
+#define CONFIG_SYS_DBAT5L              CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U              CONFIG_SYS_IBAT5U
+
+/* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
+#define CONFIG_SYS_IBAT6L              (0xE0000000 |\
+                                        BATL_PP_10 |\
+                                        BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U              (0xE0000000 |\
+                                        BATU_BL_256M |\
+                                        BATU_VS |\
+                                        BATU_VP)
+#define CONFIG_SYS_DBAT6L              CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U              CONFIG_SYS_IBAT6U
+
+#define CONFIG_SYS_IBAT7L              (0)
+#define CONFIG_SYS_IBAT7U              (0)
+#define CONFIG_SYS_DBAT7L              CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U              CONFIG_SYS_IBAT7U
+
+/*
+ * U-Boot environment setup
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_CMD_EDITENV
+#define CONFIG_CMD_JFFS2
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN         (768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN          (8 * 1024 * 1024)
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE \
+                               + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE                0x20000
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+
+#define CONFIG_NETDEV                  eth1
+#define CONFIG_HOSTNAME                ids8313
+#define CONFIG_ROOTPATH                "/opt/eldk-4.2/ppc_6xx"
+#define CONFIG_BOOTFILE                "ids8313/uImage"
+#define CONFIG_UBOOTPATH               "ids8313/u-boot.bin"
+#define CONFIG_FDTFILE                 "ids8313/ids8313.dtb"
+#define CONFIG_LOADADDR                0x400000
+#define CONFIG_CMD_ENV_FLAGS
+#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
+
+#define CONFIG_BAUDRATE                115200
+#define CONFIG_SYS_HZ                  1000
+
+/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ           (256 << 20)
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT              "=> "
+#define CONFIG_SYS_CBSIZE              1024
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE \
+                                        + sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS             16
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HUSH_PARSER         /* use "hush" command parser    */
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+
+#define CONFIG_SYS_MEMTEST_START       0x00001000
+#define CONFIG_SYS_MEMTEST_END         0x00C00000
+
+#define CONFIG_SYS_LOAD_ADDR           0x100000
+#define CONFIG_MII
+#define CONFIG_LOADS_ECHO
+#define CONFIG_TIMESTAMP
+#define CONFIG_PREBOOT                 "echo;" \
+                                       "echo Type \\\"run nfsboot\\\" " \
+                                       "to mount root filesystem over NFS;echo"
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND             "run boot_cramfs"
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_DEV               "0"
+
+/* mtdparts command line support */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_DEVICE
+#define MTDIDS_DEFAULT         "nor0=ff800000.flash,nand0=e1000000.flash"
+#define MTDPARTS_DEFAULT       "mtdparts=ff800000.flash:7m(dum)," \
+                                       "768k(BOOT-BIN)," \
+                                       "128k(BOOT-ENV),128k(BOOT-REDENV);" \
+                                       "e1000000.flash:-(ubi)"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       "netdev=" __stringify(CONFIG_NETDEV) "\0"                       \
+       "ethprime=TSEC1\0"                                              \
+       "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
+       "tftpflash=tftpboot ${loadaddr} ${uboot}; "                     \
+               "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
+               " +${filesize}; "                                       \
+               "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
+               " +${filesize}; "                                       \
+               "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)   \
+               " ${filesize}; "                                        \
+               "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
+               " +${filesize}; "                                       \
+               "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)  \
+               " ${filesize}\0"                                        \
+       "console=ttyS0\0"                                               \
+       "fdtaddr=0x780000\0"                                            \
+       "kernel_addr=ff800000\0"                                        \
+       "fdtfile=" __stringify(CONFIG_FDTFILE) "\0"                     \
+       "setbootargs=setenv bootargs "                                  \
+               "root=${rootdev} rw console=${console},"                \
+                       "${baudrate} ${othbootargs}\0"                  \
+       "setipargs=setenv bootargs root=${rootdev} rw "                 \
+                       "nfsroot=${serverip}:${rootpath} "              \
+                       "ip=${ipaddr}:${serverip}:${gatewayip}:"        \
+                       "${netmask}:${hostname}:${netdev}:off "         \
+                       "console=${console},${baudrate} ${othbootargs}\0" \
+       "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
+       "mtdids=" MTDIDS_DEFAULT "\0"                                   \
+       "mtdparts=" MTDPARTS_DEFAULT "\0"                               \
+       "\0"
+
+#define CONFIG_NFSBOOTCOMMAND                                          \
+       "setenv rootdev /dev/nfs;"                                      \
+       "run setipargs;run addmtd;"                                     \
+       "tftp ${loadaddr} ${bootfile};"                         \
+       "tftp ${fdtaddr} ${fdtfile};"                                   \
+       "fdt addr ${fdtaddr};"                                          \
+       "bootm ${loadaddr} - ${fdtaddr}"
+
+/* UBI Support */
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_PARTITIONS
+
+/* bootcount support */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_I2C
+#define CONFIG_BOOTCOUNT_ALEN  1
+#define CONFIG_SYS_BOOTCOUNT_ADDR      0x9
+
+#define CONFIG_VERSION_VARIABLE
+
+#define CONFIG_FIT
+#define CONFIG_FIT_SIGNATURE
+#define CONFIG_CMD_FDT
+#define CONFIG_CMD_HASH
+#define CONFIG_RSA
+#define CONFIG_SHA1
+#define CONFIG_SHA256
+#define CONFIG_OF_CONTROL
+
+#endif /* __CONFIG_H */