ARM: board: meson: add p201 board

This adds support for p201 reference boards

Signed-off-by: Mohammad Rasim <mohammad.rasim96@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

diff --git a/board/amlogic/p201/MAINTAINERS b/board/amlogic/p201/MAINTAINERS
new file mode 100644 (file)
index 0000000..3e84a8e
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+++ b/board/amlogic/p201/MAINTAINERS
@@ -0,0 +1,5 @@
+P201
+M:     Neil Armstrong <narmstrong@baylibre.com>
+S:     Maintained
+F:     board/amlogic/p201/
+F:     configs/p201_defconfig

diff --git a/board/amlogic/p201/Makefile b/board/amlogic/p201/Makefile
new file mode 100644 (file)
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+++ b/board/amlogic/p201/Makefile
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+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+
+obj-y  := p201.o

diff --git a/board/amlogic/p201/README.p201 b/board/amlogic/p201/README.p201
new file mode 100644 (file)
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+++ b/board/amlogic/p201/README.p201
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+U-Boot for Amlogic P201
+=======================
+
+P201 is a reference board manufactured by Amlogic with the following
+specifications:
+
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - 10/100 Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 2 x USB 2.0 Host
+ - eMMC, microSD
+ - Infrared receiver
+ - SDIO WiFi Module
+ - CVBS+Stereo Audio Jack
+
+Schematics are available from Amlogic on demand.
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - eMMC, microSD
+ - Ethernet
+ - I2C
+ - Regulators
+ - Reset controller
+ - Clock controller
+ - USB Host
+ - ADC
+
+u-boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make p201_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+ > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
+ > cd amlogic-u-boot
+ > make gxb_p201_v1_defconfig
+ > make
+ > export FIPDIR=$PWD/fip
+
+Go back to mainline U-boot source tree then :
+ > mkdir fip
+
+ > cp $FIPDIR/gxl/bl2.bin fip/
+ > cp $FIPDIR/gxl/acs.bin fip/
+ > cp $FIPDIR/gxl/bl21.bin fip/
+ > cp $FIPDIR/gxl/bl30.bin fip/
+ > cp $FIPDIR/gxl/bl301.bin fip/
+ > cp $FIPDIR/gxl/bl31.img fip/
+ > cp u-boot.bin fip/bl33.bin
+
+ > $FIPDIR/blx_fix.sh \
+       fip/bl30.bin \
+       fip/zero_tmp \
+       fip/bl30_zero.bin \
+       fip/bl301.bin \
+       fip/bl301_zero.bin \
+       fip/bl30_new.bin \
+       bl30
+
+ > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+ > $FIPDIR/blx_fix.sh \
+       fip/bl2_acs.bin \
+       fip/zero_tmp \
+       fip/bl2_zero.bin \
+       fip/bl21.bin \
+       fip/bl21_zero.bin \
+       fip/bl2_new.bin \
+       bl2
+
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+ > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
+               --output fip/u-boot.bin \
+               --bl2 fip/bl2.n.bin.sig \
+               --bl30 fip/bl30_new.bin.enc \
+               --bl31 fip/bl31.img.enc \
+               --bl33 fip/bl33.bin.enc
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

diff --git a/board/amlogic/p201/p201.c b/board/amlogic/p201/p201.c
new file mode 100644 (file)
index 0000000..ef0c65c
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+++ b/board/amlogic/p201/p201.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <environment.h>
+#include <asm/io.h>
+#include <asm/arch/gx.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
+
+#define EFUSE_SN_OFFSET                20
+#define EFUSE_SN_SIZE          16
+#define EFUSE_MAC_OFFSET       52
+#define EFUSE_MAC_SIZE         6
+
+int misc_init_r(void)
+{
+       u8 mac_addr[EFUSE_MAC_SIZE];
+       char serial[EFUSE_SN_SIZE];
+       ssize_t len;
+
+       meson_eth_init(PHY_INTERFACE_MODE_RMII, 0);
+
+       if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+               len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+                                         mac_addr, EFUSE_MAC_SIZE);
+               if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
+                       eth_env_set_enetaddr("ethaddr", mac_addr);
+       }
+
+       if (!env_get("serial#")) {
+               len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
+                       EFUSE_SN_SIZE);
+               if (len == EFUSE_SN_SIZE)
+                       env_set("serial#", serial);
+       }
+
+       return 0;
+}

diff --git a/configs/p201_defconfig b/configs/p201_defconfig
new file mode 100644 (file)
index 0000000..f6a821c
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+++ b/configs/p201_defconfig
@@ -0,0 +1,41 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" p201"
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-p201"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXBB=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SYS_BOARD="p201"