ARMv7M: Add STM32F4 support
authorrev13@wp.pl <rev13@wp.pl>
Sun, 1 Mar 2015 11:44:40 +0000 (12:44 +0100)
committerTom Rini <trini@konsulko.com>
Wed, 22 Apr 2015 16:14:55 +0000 (12:14 -0400)
Signed-off-by: Kamil Lulko <rev13@wp.pl>
Reviewed-by: Tom Rini <trini@konsulko.com>
12 files changed:
arch/arm/cpu/armv7m/Makefile
arch/arm/cpu/armv7m/stm32f4/Makefile [new file with mode: 0644]
arch/arm/cpu/armv7m/stm32f4/clock.c [new file with mode: 0644]
arch/arm/cpu/armv7m/stm32f4/flash.c [new file with mode: 0644]
arch/arm/cpu/armv7m/stm32f4/soc.c [new file with mode: 0644]
arch/arm/cpu/armv7m/stm32f4/timer.c [new file with mode: 0644]
arch/arm/include/asm/arch-stm32f4/fmc.h [new file with mode: 0644]
arch/arm/include/asm/arch-stm32f4/gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-stm32f4/stm32.h [new file with mode: 0644]
drivers/gpio/Makefile
drivers/gpio/stm32_gpio.c [new file with mode: 0644]
include/flash.h

index aff60e8102ea4b0751eb78fe37194767349eb9e5..b662e03428b9d2e744516a0a638e114844cd1f43 100644 (file)
@@ -7,3 +7,5 @@
 
 extra-y := start.o
 obj-y += cpu.o
+
+obj-$(CONFIG_STM32F4) += stm32f4/
diff --git a/arch/arm/cpu/armv7m/stm32f4/Makefile b/arch/arm/cpu/armv7m/stm32f4/Makefile
new file mode 100644 (file)
index 0000000..e982830
--- /dev/null
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2015
+# Kamil Lulko, <rev13@wp.pl>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += soc.o clock.o timer.o flash.o
diff --git a/arch/arm/cpu/armv7m/stm32f4/clock.c b/arch/arm/cpu/armv7m/stm32f4/clock.c
new file mode 100644 (file)
index 0000000..2eded1f
--- /dev/null
@@ -0,0 +1,209 @@
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * (C) Copyright 2014
+ * STMicroelectronics
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+
+#define RCC_CR_HSION           (1 << 0)
+#define RCC_CR_HSEON           (1 << 16)
+#define RCC_CR_HSERDY          (1 << 17)
+#define RCC_CR_HSEBYP          (1 << 18)
+#define RCC_CR_CSSON           (1 << 19)
+#define RCC_CR_PLLON           (1 << 24)
+#define RCC_CR_PLLRDY          (1 << 25)
+
+#define RCC_PLLCFGR_PLLM_MASK  0x3F
+#define RCC_PLLCFGR_PLLN_MASK  0x7FC0
+#define RCC_PLLCFGR_PLLP_MASK  0x30000
+#define RCC_PLLCFGR_PLLQ_MASK  0xF000000
+#define RCC_PLLCFGR_PLLSRC     (1 << 22)
+#define RCC_PLLCFGR_PLLN_SHIFT 6
+#define RCC_PLLCFGR_PLLP_SHIFT 16
+#define RCC_PLLCFGR_PLLQ_SHIFT 24
+
+#define RCC_CFGR_AHB_PSC_MASK  0xF0
+#define RCC_CFGR_APB1_PSC_MASK 0x1C00
+#define RCC_CFGR_APB2_PSC_MASK 0xE000
+#define RCC_CFGR_SW0           (1 << 0)
+#define RCC_CFGR_SW1           (1 << 1)
+#define RCC_CFGR_SW_MASK       0x3
+#define RCC_CFGR_SW_HSI                0
+#define RCC_CFGR_SW_HSE                RCC_CFGR_SW0
+#define RCC_CFGR_SW_PLL                RCC_CFGR_SW1
+#define RCC_CFGR_SWS0          (1 << 2)
+#define RCC_CFGR_SWS1          (1 << 3)
+#define RCC_CFGR_SWS_MASK      0xC
+#define RCC_CFGR_SWS_HSI       0
+#define RCC_CFGR_SWS_HSE       RCC_CFGR_SWS0
+#define RCC_CFGR_SWS_PLL       RCC_CFGR_SWS1
+#define RCC_CFGR_HPRE_SHIFT    4
+#define RCC_CFGR_PPRE1_SHIFT   10
+#define RCC_CFGR_PPRE2_SHIFT   13
+
+#define RCC_APB1ENR_PWREN      (1 << 28)
+
+#define PWR_CR_VOS0            (1 << 14)
+#define PWR_CR_VOS1            (1 << 15)
+#define PWR_CR_VOS_MASK                0xC000
+#define PWR_CR_VOS_SCALE_MODE_1        (PWR_CR_VOS0 | PWR_CR_VOS1)
+#define PWR_CR_VOS_SCALE_MODE_2        (PWR_CR_VOS1)
+#define PWR_CR_VOS_SCALE_MODE_3        (PWR_CR_VOS0)
+
+#define FLASH_ACR_WS(n)                n
+#define FLASH_ACR_PRFTEN       (1 << 8)
+#define FLASH_ACR_ICEN         (1 << 9)
+#define FLASH_ACR_DCEN         (1 << 10)
+
+struct pll_psc {
+       u8      pll_m;
+       u16     pll_n;
+       u8      pll_p;
+       u8      pll_q;
+       u8      ahb_psc;
+       u8      apb1_psc;
+       u8      apb2_psc;
+};
+
+#define AHB_PSC_1              0
+#define AHB_PSC_2              0x8
+#define AHB_PSC_4              0x9
+#define AHB_PSC_8              0xA
+#define AHB_PSC_16             0xB
+#define AHB_PSC_64             0xC
+#define AHB_PSC_128            0xD
+#define AHB_PSC_256            0xE
+#define AHB_PSC_512            0xF
+
+#define APB_PSC_1              0
+#define APB_PSC_2              0x4
+#define APB_PSC_4              0x5
+#define APB_PSC_8              0x6
+#define APB_PSC_16             0x7
+
+#if !defined(CONFIG_STM32_HSE_HZ)
+#error "CONFIG_STM32_HSE_HZ not defined!"
+#else
+#if (CONFIG_STM32_HSE_HZ == 8000000)
+struct pll_psc pll_psc_168 = {
+       .pll_m = 8,
+       .pll_n = 336,
+       .pll_p = 2,
+       .pll_q = 7,
+       .ahb_psc = AHB_PSC_1,
+       .apb1_psc = APB_PSC_4,
+       .apb2_psc = APB_PSC_2
+};
+#else
+#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
+#endif
+#endif
+
+int configure_clocks(void)
+{
+       /* Reset RCC configuration */
+       setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
+       writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
+       clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
+               | RCC_CR_PLLON));
+       writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
+       clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
+       writel(0, &STM32_RCC->cir); /* Disable all interrupts */
+
+       /* Configure for HSE+PLL operation */
+       setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
+       while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
+               ;
+
+       /* Enable high performance mode, System frequency up to 168 MHz */
+       setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
+       writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
+
+       setbits_le32(&STM32_RCC->cfgr, ((
+               pll_psc_168.ahb_psc << RCC_CFGR_HPRE_SHIFT)
+               | (pll_psc_168.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
+               | (pll_psc_168.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
+
+       writel(pll_psc_168.pll_m
+               | (pll_psc_168.pll_n << RCC_PLLCFGR_PLLN_SHIFT)
+               | (((pll_psc_168.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT)
+               | (pll_psc_168.pll_q << RCC_PLLCFGR_PLLQ_SHIFT),
+               &STM32_RCC->pllcfgr);
+       setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC);
+
+       setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
+
+       while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
+               ;
+
+       /* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
+       writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
+               | FLASH_ACR_DCEN, &STM32_FLASH->acr);
+
+       clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
+       setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
+
+       while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
+                       RCC_CFGR_SWS_PLL)
+               ;
+
+       return 0;
+}
+
+unsigned long clock_get(enum clock clck)
+{
+       u32 sysclk = 0;
+       u32 shift = 0;
+       /* Prescaler table lookups for clock computation */
+       u8 ahb_psc_table[16] = {
+               0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
+       };
+       u8 apb_psc_table[8] = {
+               0, 0, 0, 0, 1, 2, 3, 4
+       };
+
+       if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
+                       RCC_CFGR_SWS_PLL) {
+               u16 pllm, plln, pllp;
+               pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
+               plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
+                       >> RCC_PLLCFGR_PLLN_SHIFT);
+               pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
+                       >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
+               sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
+       }
+
+       switch (clck) {
+       case CLOCK_CORE:
+               return sysclk;
+               break;
+       case CLOCK_AHB:
+               shift = ahb_psc_table[(
+                       (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
+                       >> RCC_CFGR_HPRE_SHIFT)];
+               return sysclk >>= shift;
+               break;
+       case CLOCK_APB1:
+               shift = apb_psc_table[(
+                       (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
+                       >> RCC_CFGR_PPRE1_SHIFT)];
+               return sysclk >>= shift;
+               break;
+       case CLOCK_APB2:
+               shift = apb_psc_table[(
+                       (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
+                       >> RCC_CFGR_PPRE2_SHIFT)];
+               return sysclk >>= shift;
+               break;
+       default:
+               return 0;
+               break;
+       }
+}
diff --git a/arch/arm/cpu/armv7m/stm32f4/flash.c b/arch/arm/cpu/armv7m/stm32f4/flash.c
new file mode 100644 (file)
index 0000000..e5c6111
--- /dev/null
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+
+#define STM32_FLASH_KEY1       0x45670123
+#define STM32_FLASH_KEY2       0xCDEF89AB
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
+       [0 ... 3] =     16 * 1024,
+       [4] =           64 * 1024,
+       [5 ... 11] =    128 * 1024
+};
+
+static void stm32f4_flash_lock(u8 lock)
+{
+       if (lock) {
+               setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_LOCK);
+       } else {
+               writel(STM32_FLASH_KEY1, &STM32_FLASH->key);
+               writel(STM32_FLASH_KEY2, &STM32_FLASH->key);
+       }
+}
+
+unsigned long flash_init(void)
+{
+       unsigned long total_size = 0;
+       u8 i, j;
+
+       for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+               flash_info[i].flash_id = FLASH_STM32F4;
+               flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+               flash_info[i].start[0] = CONFIG_SYS_FLASH_BASE + (i << 20);
+               flash_info[i].size = sect_sz_kb[0];
+               for (j = 1; j < CONFIG_SYS_MAX_FLASH_SECT; j++) {
+                       flash_info[i].start[j] = flash_info[i].start[j - 1]
+                               + (sect_sz_kb[j - 1]);
+                       flash_info[i].size += sect_sz_kb[j];
+               }
+               total_size += flash_info[i].size;
+       }
+
+       return total_size;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+       int i;
+
+       if (info->flash_id == FLASH_UNKNOWN) {
+               printf("missing or unknown FLASH type\n");
+               return;
+       } else if (info->flash_id == FLASH_STM32F4) {
+               printf("STM32F4 Embedded Flash\n");
+       }
+
+       printf("  Size: %ld MB in %d Sectors\n",
+              info->size >> 20, info->sector_count);
+
+       printf("  Sector Start Addresses:");
+       for (i = 0; i < info->sector_count; ++i) {
+               if ((i % 5) == 0)
+                       printf("\n   ");
+               printf(" %08lX%s",
+                      info->start[i],
+                       info->protect[i] ? " (RO)" : "     ");
+       }
+       printf("\n");
+       return;
+}
+
+int flash_erase(flash_info_t *info, int first, int last)
+{
+       u8 bank = 0xFF;
+       int i;
+
+       for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+               if (info == &flash_info[i]) {
+                       bank = i;
+                       break;
+               }
+       }
+       if (bank == 0xFF)
+               return -1;
+
+       stm32f4_flash_lock(0);
+
+       for (i = first; i <= last; i++) {
+               while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
+                       ;
+
+               if (bank == 0) {
+                       setbits_le32(&STM32_FLASH->cr,
+                                    (i << STM32_FLASH_CR_SNB_OFFSET));
+               } else if (bank == 1) {
+                       setbits_le32(&STM32_FLASH->cr,
+                                    ((0x10 | i) << STM32_FLASH_CR_SNB_OFFSET));
+               } else {
+                       stm32f4_flash_lock(1);
+                       return -1;
+               }
+               setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
+               setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_STRT);
+
+               while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
+                       ;
+
+               clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
+               stm32f4_flash_lock(1);
+       }
+
+       return 0;
+}
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+       ulong i;
+
+       while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
+               ;
+
+       stm32f4_flash_lock(0);
+
+       setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG);
+       /* To make things simple use byte writes only */
+       for (i = 0; i < cnt; i++) {
+               *(uchar *)(addr + i) = src[i];
+               while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
+                       ;
+       }
+       clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG);
+       stm32f4_flash_lock(1);
+
+       return 0;
+}
diff --git a/arch/arm/cpu/armv7m/stm32f4/soc.c b/arch/arm/cpu/armv7m/stm32f4/soc.c
new file mode 100644 (file)
index 0000000..202a126
--- /dev/null
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+#include <asm/arch/stm32.h>
+
+u32 get_cpu_rev(void)
+{
+       return 0;
+}
+
+int arch_cpu_init(void)
+{
+       configure_clocks();
+
+       /*
+        * Configure the memory protection unit (MPU) to allow full access to
+        * the whole 4GB address space.
+        */
+       writel(0, &V7M_MPU->rnr);
+       writel(0, &V7M_MPU->rbar);
+       writel((V7M_MPU_RASR_AP_RW_RW | V7M_MPU_RASR_SIZE_4GB
+               | V7M_MPU_RASR_EN), &V7M_MPU->rasr);
+       writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl);
+
+       return 0;
+}
+
+void s_init(void)
+{
+}
diff --git a/arch/arm/cpu/armv7m/stm32f4/timer.c b/arch/arm/cpu/armv7m/stm32f4/timer.c
new file mode 100644 (file)
index 0000000..102ae6d
--- /dev/null
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+#include <asm/arch/stm32.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define STM32_TIM2_BASE        (STM32_APB1PERIPH_BASE + 0x0000)
+
+#define RCC_APB1ENR_TIM2EN     (1 << 0)
+
+struct stm32_tim2_5 {
+       u32 cr1;
+       u32 cr2;
+       u32 smcr;
+       u32 dier;
+       u32 sr;
+       u32 egr;
+       u32 ccmr1;
+       u32 ccmr2;
+       u32 ccer;
+       u32 cnt;
+       u32 psc;
+       u32 arr;
+       u32 reserved1;
+       u32 ccr1;
+       u32 ccr2;
+       u32 ccr3;
+       u32 ccr4;
+       u32 reserved2;
+       u32 dcr;
+       u32 dmar;
+       u32 or;
+};
+
+#define TIM_CR1_CEN    (1 << 0)
+
+#define TIM_EGR_UG     (1 << 0)
+
+int timer_init(void)
+{
+       struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
+
+       setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
+
+       if (clock_get(CLOCK_AHB) == clock_get(CLOCK_APB1))
+               writel((clock_get(CLOCK_APB1) / CONFIG_SYS_HZ_CLOCK) - 1,
+                      &tim->psc);
+       else
+               writel(((clock_get(CLOCK_APB1) * 2) / CONFIG_SYS_HZ_CLOCK) - 1,
+                      &tim->psc);
+
+       writel(0xFFFFFFFF, &tim->arr);
+       writel(TIM_CR1_CEN, &tim->cr1);
+       setbits_le32(&tim->egr, TIM_EGR_UG);
+
+       gd->arch.tbl = 0;
+       gd->arch.tbu = 0;
+       gd->arch.lastinc = 0;
+
+       return 0;
+}
+
+ulong get_timer(ulong base)
+{
+       return (get_ticks() / (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)) - base;
+}
+
+unsigned long long get_ticks(void)
+{
+       struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
+       u32 now;
+
+       now = readl(&tim->cnt);
+
+       if (now >= gd->arch.lastinc)
+               gd->arch.tbl += (now - gd->arch.lastinc);
+       else
+               gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
+
+       gd->arch.lastinc = now;
+
+       return gd->arch.tbl;
+}
+
+void reset_timer(void)
+{
+       struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
+
+       gd->arch.lastinc = readl(&tim->cnt);
+       gd->arch.tbl = 0;
+}
+
+/* delay x useconds */
+void __udelay(ulong usec)
+{
+       unsigned long long start;
+
+       start = get_ticks();            /* get current timestamp */
+       while ((get_ticks() - start) < usec)
+               ;                       /* loop till time has passed */
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+       return CONFIG_SYS_HZ_CLOCK;
+}
diff --git a/arch/arm/include/asm/arch-stm32f4/fmc.h b/arch/arm/include/asm/arch-stm32f4/fmc.h
new file mode 100644 (file)
index 0000000..4ab3031
--- /dev/null
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2013
+ * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _MACH_FMC_H_
+#define _MACH_FMC_H_
+
+struct stm32_fmc_regs {
+       u32 sdcr1;      /* Control register 1 */
+       u32 sdcr2;      /* Control register 2 */
+       u32 sdtr1;      /* Timing register 1 */
+       u32 sdtr2;      /* Timing register 2 */
+       u32 sdcmr;      /* Mode register */
+       u32 sdrtr;      /* Refresh timing register */
+       u32 sdsr;       /* Status register */
+};
+
+/*
+ * FMC registers base
+ */
+#define STM32_SDRAM_FMC_BASE   0xA0000140
+#define STM32_SDRAM_FMC                ((struct stm32_fmc_regs *)STM32_SDRAM_FMC_BASE)
+
+/* Control register SDCR */
+#define FMC_SDCR_RPIPE_SHIFT   13      /* RPIPE bit shift */
+#define FMC_SDCR_RBURST_SHIFT  12      /* RBURST bit shift */
+#define FMC_SDCR_SDCLK_SHIFT   10      /* SDRAM clock divisor shift */
+#define FMC_SDCR_WP_SHIFT      9       /* Write protection shift */
+#define FMC_SDCR_CAS_SHIFT     7       /* CAS latency shift */
+#define FMC_SDCR_NB_SHIFT      6       /* Number of banks shift */
+#define FMC_SDCR_MWID_SHIFT    4       /* Memory width shift */
+#define FMC_SDCR_NR_SHIFT      2       /* Number of row address bits shift */
+#define FMC_SDCR_NC_SHIFT      0       /* Number of col address bits shift */
+
+/* Timings register SDTR */
+#define FMC_SDTR_TMRD_SHIFT    0       /* Load mode register to active */
+#define FMC_SDTR_TXSR_SHIFT    4       /* Exit self-refresh time */
+#define FMC_SDTR_TRAS_SHIFT    8       /* Self-refresh time */
+#define FMC_SDTR_TRC_SHIFT     12      /* Row cycle delay */
+#define FMC_SDTR_TWR_SHIFT     16      /* Recovery delay */
+#define FMC_SDTR_TRP_SHIFT     20      /* Row precharge delay */
+#define FMC_SDTR_TRCD_SHIFT    24      /* Row-to-column delay */
+
+
+#define FMC_SDCMR_NRFS_SHIFT   5
+
+#define FMC_SDCMR_MODE_NORMAL          0
+#define FMC_SDCMR_MODE_START_CLOCK     1
+#define FMC_SDCMR_MODE_PRECHARGE       2
+#define FMC_SDCMR_MODE_AUTOREFRESH     3
+#define FMC_SDCMR_MODE_WRITE_MODE      4
+#define FMC_SDCMR_MODE_SELFREFRESH     5
+#define FMC_SDCMR_MODE_POWERDOWN       6
+
+#define FMC_SDCMR_BANK_1               (1 << 4)
+#define FMC_SDCMR_BANK_2               (1 << 3)
+
+#define FMC_SDCMR_MODE_REGISTER_SHIFT  9
+
+#define FMC_SDSR_BUSY                  (1 << 5)
+
+#define FMC_BUSY_WAIT()                do { \
+               __asm__ __volatile__ ("dsb" : : : "memory"); \
+               while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \
+                       ; \
+       } while (0)
+
+
+#endif /* _MACH_FMC_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f4/gpio.h b/arch/arm/include/asm/arch-stm32f4/gpio.h
new file mode 100644 (file)
index 0000000..7cd866e
--- /dev/null
@@ -0,0 +1,116 @@
+/*
+ * (C) Copyright 2011
+ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _STM32_GPIO_H_
+#define _STM32_GPIO_H_
+
+enum stm32_gpio_port {
+       STM32_GPIO_PORT_A = 0,
+       STM32_GPIO_PORT_B,
+       STM32_GPIO_PORT_C,
+       STM32_GPIO_PORT_D,
+       STM32_GPIO_PORT_E,
+       STM32_GPIO_PORT_F,
+       STM32_GPIO_PORT_G,
+       STM32_GPIO_PORT_H,
+       STM32_GPIO_PORT_I
+};
+
+enum stm32_gpio_pin {
+       STM32_GPIO_PIN_0 = 0,
+       STM32_GPIO_PIN_1,
+       STM32_GPIO_PIN_2,
+       STM32_GPIO_PIN_3,
+       STM32_GPIO_PIN_4,
+       STM32_GPIO_PIN_5,
+       STM32_GPIO_PIN_6,
+       STM32_GPIO_PIN_7,
+       STM32_GPIO_PIN_8,
+       STM32_GPIO_PIN_9,
+       STM32_GPIO_PIN_10,
+       STM32_GPIO_PIN_11,
+       STM32_GPIO_PIN_12,
+       STM32_GPIO_PIN_13,
+       STM32_GPIO_PIN_14,
+       STM32_GPIO_PIN_15
+};
+
+enum stm32_gpio_mode {
+       STM32_GPIO_MODE_IN = 0,
+       STM32_GPIO_MODE_OUT,
+       STM32_GPIO_MODE_AF,
+       STM32_GPIO_MODE_AN
+};
+
+enum stm32_gpio_otype {
+       STM32_GPIO_OTYPE_PP = 0,
+       STM32_GPIO_OTYPE_OD
+};
+
+enum stm32_gpio_speed {
+       STM32_GPIO_SPEED_2M = 0,
+       STM32_GPIO_SPEED_25M,
+       STM32_GPIO_SPEED_50M,
+       STM32_GPIO_SPEED_100M
+};
+
+enum stm32_gpio_pupd {
+       STM32_GPIO_PUPD_NO = 0,
+       STM32_GPIO_PUPD_UP,
+       STM32_GPIO_PUPD_DOWN
+};
+
+enum stm32_gpio_af {
+       STM32_GPIO_AF0 = 0,
+       STM32_GPIO_AF1,
+       STM32_GPIO_AF2,
+       STM32_GPIO_AF3,
+       STM32_GPIO_AF4,
+       STM32_GPIO_AF5,
+       STM32_GPIO_AF6,
+       STM32_GPIO_AF7,
+       STM32_GPIO_AF8,
+       STM32_GPIO_AF9,
+       STM32_GPIO_AF10,
+       STM32_GPIO_AF11,
+       STM32_GPIO_AF12,
+       STM32_GPIO_AF13,
+       STM32_GPIO_AF14,
+       STM32_GPIO_AF15
+};
+
+struct stm32_gpio_dsc {
+       enum stm32_gpio_port    port;
+       enum stm32_gpio_pin     pin;
+};
+
+struct stm32_gpio_ctl {
+       enum stm32_gpio_mode    mode;
+       enum stm32_gpio_otype   otype;
+       enum stm32_gpio_speed   speed;
+       enum stm32_gpio_pupd    pupd;
+       enum stm32_gpio_af      af;
+};
+
+static inline unsigned stm32_gpio_to_port(unsigned gpio)
+{
+       return gpio / 16;
+}
+
+static inline unsigned stm32_gpio_to_pin(unsigned gpio)
+{
+       return gpio % 16;
+}
+
+int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc,
+               const struct stm32_gpio_ctl *gpio_ctl);
+int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state);
+
+#endif /* _STM32_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h
new file mode 100644 (file)
index 0000000..a9f88db
--- /dev/null
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2011
+ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _MACH_STM32_H_
+#define _MACH_STM32_H_
+
+/*
+ * Peripheral memory map
+ */
+#define STM32_PERIPH_BASE      0x40000000
+#define STM32_APB1PERIPH_BASE  (STM32_PERIPH_BASE + 0x00000000)
+#define STM32_APB2PERIPH_BASE  (STM32_PERIPH_BASE + 0x00010000)
+#define STM32_AHB1PERIPH_BASE  (STM32_PERIPH_BASE + 0x00020000)
+#define STM32_AHB2PERIPH_BASE  (STM32_PERIPH_BASE + 0x10000000)
+
+#define STM32_BUS_MASK         0xFFFF0000
+
+/*
+ * Register maps
+ */
+struct stm32_rcc_regs {
+       u32 cr;         /* RCC clock control */
+       u32 pllcfgr;    /* RCC PLL configuration */
+       u32 cfgr;       /* RCC clock configuration */
+       u32 cir;        /* RCC clock interrupt */
+       u32 ahb1rstr;   /* RCC AHB1 peripheral reset */
+       u32 ahb2rstr;   /* RCC AHB2 peripheral reset */
+       u32 ahb3rstr;   /* RCC AHB3 peripheral reset */
+       u32 rsv0;
+       u32 apb1rstr;   /* RCC APB1 peripheral reset */
+       u32 apb2rstr;   /* RCC APB2 peripheral reset */
+       u32 rsv1[2];
+       u32 ahb1enr;    /* RCC AHB1 peripheral clock enable */
+       u32 ahb2enr;    /* RCC AHB2 peripheral clock enable */
+       u32 ahb3enr;    /* RCC AHB3 peripheral clock enable */
+       u32 rsv2;
+       u32 apb1enr;    /* RCC APB1 peripheral clock enable */
+       u32 apb2enr;    /* RCC APB2 peripheral clock enable */
+       u32 rsv3[2];
+       u32 ahb1lpenr;  /* RCC AHB1 periph clk enable in low pwr mode */
+       u32 ahb2lpenr;  /* RCC AHB2 periph clk enable in low pwr mode */
+       u32 ahb3lpenr;  /* RCC AHB3 periph clk enable in low pwr mode */
+       u32 rsv4;
+       u32 apb1lpenr;  /* RCC APB1 periph clk enable in low pwr mode */
+       u32 apb2lpenr;  /* RCC APB2 periph clk enable in low pwr mode */
+       u32 rsv5[2];
+       u32 bdcr;       /* RCC Backup domain control */
+       u32 csr;        /* RCC clock control & status */
+       u32 rsv6[2];
+       u32 sscgr;      /* RCC spread spectrum clock generation */
+       u32 plli2scfgr; /* RCC PLLI2S configuration */
+       u32 pllsaicfgr;
+       u32 dckcfgr;
+};
+
+struct stm32_pwr_regs {
+       u32 cr;
+       u32 csr;
+};
+
+struct stm32_flash_regs {
+       u32 acr;
+       u32 key;
+       u32 optkeyr;
+       u32 sr;
+       u32 cr;
+       u32 optcr;
+       u32 optcr1;
+};
+
+/*
+ * Registers access macros
+ */
+#define STM32_RCC_BASE         (STM32_AHB1PERIPH_BASE + 0x3800)
+#define STM32_RCC              ((struct stm32_rcc_regs *)STM32_RCC_BASE)
+
+#define STM32_PWR_BASE         (STM32_APB1PERIPH_BASE + 0x7000)
+#define STM32_PWR              ((struct stm32_pwr_regs *)STM32_PWR_BASE)
+
+#define STM32_FLASH_BASE       (STM32_AHB1PERIPH_BASE + 0x3C00)
+#define STM32_FLASH            ((struct stm32_flash_regs *)STM32_FLASH_BASE)
+
+#define STM32_FLASH_SR_BSY             (1 << 16)
+
+#define STM32_FLASH_CR_PG              (1 << 0)
+#define STM32_FLASH_CR_SER             (1 << 1)
+#define STM32_FLASH_CR_STRT            (1 << 16)
+#define STM32_FLASH_CR_LOCK            (1 << 31)
+#define STM32_FLASH_CR_SNB_OFFSET      3
+
+enum clock {
+       CLOCK_CORE,
+       CLOCK_AHB,
+       CLOCK_APB1,
+       CLOCK_APB2
+};
+
+int configure_clocks(void);
+unsigned long clock_get(enum clock clck);
+
+#endif /* _MACH_STM32_H_ */
index 85f71c5d4a773172ece61eecc3f9af6640231925..8ca8b05ebff8c26aef5ec356f1a455137377f29b 100644 (file)
@@ -42,3 +42,4 @@ obj-$(CONFIG_TCA642X)         += tca642x.o
 oby-$(CONFIG_SX151X)           += sx151x.o
 obj-$(CONFIG_SUNXI_GPIO)       += sunxi_gpio.o
 obj-$(CONFIG_LPC32XX_GPIO)     += lpc32xx_gpio.o
+obj-$(CONFIG_STM32_GPIO)       += stm32_gpio.o
diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c
new file mode 100644 (file)
index 0000000..d3497e9
--- /dev/null
@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2011
+ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define STM32_GPIOA_BASE       (STM32_AHB1PERIPH_BASE + 0x0000)
+#define STM32_GPIOB_BASE       (STM32_AHB1PERIPH_BASE + 0x0400)
+#define STM32_GPIOC_BASE       (STM32_AHB1PERIPH_BASE + 0x0800)
+#define STM32_GPIOD_BASE       (STM32_AHB1PERIPH_BASE + 0x0C00)
+#define STM32_GPIOE_BASE       (STM32_AHB1PERIPH_BASE + 0x1000)
+#define STM32_GPIOF_BASE       (STM32_AHB1PERIPH_BASE + 0x1400)
+#define STM32_GPIOG_BASE       (STM32_AHB1PERIPH_BASE + 0x1800)
+#define STM32_GPIOH_BASE       (STM32_AHB1PERIPH_BASE + 0x1C00)
+#define STM32_GPIOI_BASE       (STM32_AHB1PERIPH_BASE + 0x2000)
+
+static const unsigned long io_base[] = {
+       STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
+       STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
+       STM32_GPIOG_BASE, STM32_GPIOH_BASE, STM32_GPIOI_BASE
+};
+
+struct stm32_gpio_regs {
+       u32 moder;      /* GPIO port mode */
+       u32 otyper;     /* GPIO port output type */
+       u32 ospeedr;    /* GPIO port output speed */
+       u32 pupdr;      /* GPIO port pull-up/pull-down */
+       u32 idr;        /* GPIO port input data */
+       u32 odr;        /* GPIO port output data */
+       u32 bsrr;       /* GPIO port bit set/reset */
+       u32 lckr;       /* GPIO port configuration lock */
+       u32 afr[2];     /* GPIO alternate function */
+};
+
+#define CHECK_DSC(x)   (!x || x->port > 8 || x->pin > 15)
+#define CHECK_CTL(x)   (!x || x->af > 15 || x->mode > 3 || x->otype > 1 || \
+                       x->pupd > 2 || x->speed > 3)
+
+int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
+               const struct stm32_gpio_ctl *ctl)
+{
+       struct stm32_gpio_regs *gpio_regs;
+       u32 i;
+       int rv;
+
+       if (CHECK_DSC(dsc)) {
+               rv = -EINVAL;
+               goto out;
+       }
+       if (CHECK_CTL(ctl)) {
+               rv = -EINVAL;
+               goto out;
+       }
+
+       gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
+
+       setbits_le32(&STM32_RCC->ahb1enr, 1 << dsc->port);
+
+       i = (dsc->pin & 0x07) * 4;
+       clrbits_le32(&gpio_regs->afr[dsc->pin >> 3], (0xF << i));
+       setbits_le32(&gpio_regs->afr[dsc->pin >> 3], ctl->af << i);
+
+       i = dsc->pin * 2;
+
+       clrbits_le32(&gpio_regs->moder, (0x3 << i));
+       setbits_le32(&gpio_regs->moder, ctl->mode << i);
+
+       clrbits_le32(&gpio_regs->otyper, (0x3 << i));
+       setbits_le32(&gpio_regs->otyper, ctl->otype << i);
+
+       clrbits_le32(&gpio_regs->ospeedr, (0x3 << i));
+       setbits_le32(&gpio_regs->ospeedr, ctl->speed << i);
+
+       clrbits_le32(&gpio_regs->pupdr, (0x3 << i));
+       setbits_le32(&gpio_regs->pupdr, ctl->pupd << i);
+
+       rv = 0;
+out:
+       return rv;
+}
+
+int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state)
+{
+       struct stm32_gpio_regs  *gpio_regs;
+       int rv;
+
+       if (CHECK_DSC(dsc)) {
+               rv = -EINVAL;
+               goto out;
+       }
+
+       gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
+
+       if (state)
+               writel(1 << dsc->pin, &gpio_regs->bsrr);
+       else
+               writel(1 << (dsc->pin + 16), &gpio_regs->bsrr);
+
+       rv = 0;
+out:
+       return rv;
+}
+
+int stm32_gpin_get(const struct stm32_gpio_dsc *dsc)
+{
+       struct stm32_gpio_regs  *gpio_regs;
+       int rv;
+
+       if (CHECK_DSC(dsc)) {
+               rv = -EINVAL;
+               goto out;
+       }
+
+       gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
+       rv = readl(&gpio_regs->idr) & (1 << dsc->pin);
+out:
+       return rv;
+}
+
+/* Common GPIO API */
+
+int gpio_request(unsigned gpio, const char *label)
+{
+       return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+       return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+       struct stm32_gpio_dsc dsc;
+       struct stm32_gpio_ctl ctl;
+
+       dsc.port = stm32_gpio_to_port(gpio);
+       dsc.pin = stm32_gpio_to_pin(gpio);
+       ctl.af = STM32_GPIO_AF0;
+       ctl.mode = STM32_GPIO_MODE_IN;
+       ctl.pupd = STM32_GPIO_PUPD_NO;
+       ctl.speed = STM32_GPIO_SPEED_50M;
+
+       return stm32_gpio_config(&dsc, &ctl);
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+       struct stm32_gpio_dsc dsc;
+       struct stm32_gpio_ctl ctl;
+       int res;
+
+       dsc.port = stm32_gpio_to_port(gpio);
+       dsc.pin = stm32_gpio_to_pin(gpio);
+       ctl.af = STM32_GPIO_AF0;
+       ctl.mode = STM32_GPIO_MODE_OUT;
+       ctl.otype = STM32_GPIO_OTYPE_PP;
+       ctl.pupd = STM32_GPIO_PUPD_NO;
+       ctl.speed = STM32_GPIO_SPEED_50M;
+
+       res = stm32_gpio_config(&dsc, &ctl);
+       if (res < 0)
+               goto out;
+       res = stm32_gpout_set(&dsc, value);
+out:
+       return res;
+}
+
+int gpio_get_value(unsigned gpio)
+{
+       struct stm32_gpio_dsc dsc;
+
+       dsc.port = stm32_gpio_to_port(gpio);
+       dsc.pin = stm32_gpio_to_pin(gpio);
+
+       return stm32_gpin_get(&dsc);
+}
+
+int gpio_set_value(unsigned gpio, int value)
+{
+       struct stm32_gpio_dsc dsc;
+
+       dsc.port = stm32_gpio_to_port(gpio);
+       dsc.pin = stm32_gpio_to_pin(gpio);
+
+       return stm32_gpout_set(&dsc, value);
+}
index 30aa080b883eb0ec1febcb067965cea758491bfd..48aa3a5f8e387ebcc23cf0b008352da3f9dfbca2 100644 (file)
@@ -459,6 +459,8 @@ extern flash_info_t *flash_get_info(ulong base);
 #define FLASH_S29GL064M 0x00F0         /* Spansion S29GL064M-R6                */
 #define FLASH_S29GL128N 0x00F1         /* Spansion S29GL128N                   */
 
+#define FLASH_STM32F4  0x00F2          /* STM32F4 Embedded Flash */
+
 #define FLASH_UNKNOWN  0xFFFF          /* unknown flash type                   */