display5: ddr: Enable support for DDR3 auto calibration

This code performs DDR3 memory calibration for display5 board.

Signed-off-by: Lukasz Majewski <lukma@denx.de>

diff --git a/board/liebherr/display5/spl.c b/board/liebherr/display5/spl.c
index 5c6b8bff38acde9d32fdf3b3aa9cfafa8886c840..0c0172e201091714ab89db78cf2c712d61e19469 100644 (file)
--- a/board/liebherr/display5/spl.c
+++ b/board/liebherr/display5/spl.c
@@ -117,6 +117,49 @@ static void ccgr_init(void)
        writel(0x000003FF, &ccm->CCGR6);
 }
 
+#ifdef CONFIG_MX6_DDRCAL
+static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
+{
+       struct mx6_mmdc_calibration calibration = {0};
+
+       mmdc_read_calibration(sysinfo, &calibration);
+
+       debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
+       debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
+       debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
+       debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
+       debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
+       debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
+       debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
+       debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
+       debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
+       debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
+       debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
+       debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
+}
+
+static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
+{
+       int ret;
+
+       /* Perform DDR DRAM calibration */
+       udelay(100);
+       ret = mmdc_do_write_level_calibration(sysinfo);
+       if (ret) {
+               printf("DDR: Write level calibration error [%d]\n", ret);
+               return;
+       }
+
+       ret = mmdc_do_dqs_calibration(sysinfo);
+       if (ret) {
+               printf("DDR: DQS calibration error [%d]\n", ret);
+               return;
+       }
+
+       spl_dram_print_cal(sysinfo);
+}
+#endif /* CONFIG_MX6_DDRCAL */
+
 static void spl_dram_init(void)
 {
        struct mx6_ddr_sysinfo sysinfo = {
@@ -143,6 +186,10 @@ static void spl_dram_init(void)
 
        mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
        mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
+
+#ifdef CONFIG_MX6_DDRCAL
+       spl_dram_perform_cal(&sysinfo);
+#endif
 }
 
 #ifdef CONFIG_SPL_SPI_SUPPORT

diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index aaf8529628dc1ae7c2f1e930e5a3979c3dc0fed3..6ae6d05659a696d15c91a89dd04dfc52de26662b 100644 (file)
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_MX6_DDRCAL=y
 CONFIG_TARGET_DISPLAY5=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y