ARM: vf610: Initial integration for Colibri VF50/VF61
authorSanchayan Maity <maitysanchayan@gmail.com>
Wed, 15 Apr 2015 10:54:26 +0000 (16:24 +0530)
committerTom Rini <trini@konsulko.com>
Thu, 23 Apr 2015 18:56:09 +0000 (14:56 -0400)
This adds initial support for Colibri VF50/VF61 based on Freescale
Vybrid SoC.

- CPU clocked at 396/500 MHz
- DDR3 at 396MHz
  - for VF50, use PLL2 as memory clock (synchronous mode)
  - for VF61, use PLL1 as memory clock (asynchronous mode)
- Console on UART0 (Colibri UART_A)
- Ethernet on FEC1
- PLL5 based RMII clocking (E.g. No external crystal)
- UART_A and UART_C I/O muxing
- Boot from NAND by default

Tested on Colibri VF50/VF61 booting using serial loader over UART.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Acked-by: Stefan Agner <stefan@agner.ch>
arch/arm/Kconfig
arch/arm/include/asm/arch-vf610/imx-regs.h
board/toradex/colibri_vf/Kconfig [new file with mode: 0644]
board/toradex/colibri_vf/MAINTAINERS [new file with mode: 0644]
board/toradex/colibri_vf/Makefile [new file with mode: 0644]
board/toradex/colibri_vf/colibri_vf.c [new file with mode: 0644]
board/toradex/colibri_vf/imximage.cfg [new file with mode: 0644]
configs/colibri_vf_defconfig [new file with mode: 0644]
include/configs/colibri_vf.h [new file with mode: 0644]

index 7abcff12e06660030dccc1c5a274959f0f1feec5..b39bb4f532f75181da14d8d1d05464dcf50a8b58 100644 (file)
@@ -640,6 +640,10 @@ config TARGET_VF610TWR
        bool "Support vf610twr"
        select CPU_V7
 
+config TARGET_COLIBRI_VF
+       bool "Support Colibri VF50/61"
+       select CPU_V7
+
 config ZYNQ
        bool "Xilinx Zynq Platform"
        select CPU_V7
@@ -914,6 +918,7 @@ source "board/ti/ti814x/Kconfig"
 source "board/ti/ti816x/Kconfig"
 source "board/timll/devkit3250/Kconfig"
 source "board/toradex/colibri_pxa270/Kconfig"
+source "board/toradex/colibri_vf/Kconfig"
 source "board/tqc/tqma6/Kconfig"
 source "board/trizepsiv/Kconfig"
 source "board/ttcontrol/vision2/Kconfig"
index a5908ca1028e55399600fd4395bb2e3d36b52506..bf4197114816196df3be57b8314a0ae9ec5e8317 100644 (file)
 #define SRC_SRSR_WDOG_M4                               (0x1 << 4)
 #define SRC_SRSR_WDOG_A5                               (0x1 << 3)
 #define SRC_SRSR_POR_RST                               (0x1 << 0)
+#define SRC_SBMR2_BMOD_MASK             (0x3 << 24)
+#define SRC_SBMR2_BMOD_SHIFT            24
+#define SRC_SBMR2_BMOD_FUSES            0x0
+#define SRC_SBMR2_BMOD_SERIAL           0x1
+#define SRC_SBMR2_BMOD_RCON             0x2
 
 /* Slow Clock Source Controller Module (SCSC) */
 #define SCSC_SOSC_CTR_SOSC_EN            0x1
diff --git a/board/toradex/colibri_vf/Kconfig b/board/toradex/colibri_vf/Kconfig
new file mode 100644 (file)
index 0000000..2c3cb30
--- /dev/null
@@ -0,0 +1,18 @@
+if TARGET_COLIBRI_VF
+
+config SYS_CPU
+       default "armv7"
+
+config SYS_BOARD
+       default "colibri_vf"
+
+config SYS_VENDOR
+       default "toradex"
+
+config SYS_SOC
+       default "vf610"
+
+config SYS_CONFIG_NAME
+       default "colibri_vf"
+
+endif
diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS
new file mode 100644 (file)
index 0000000..551c575
--- /dev/null
@@ -0,0 +1,6 @@
+Colibri VFxx
+M:     Stefan Agner <stefan.agner@toradex.com>
+S:     Maintained
+F:     board/toradex/colibri_vf/
+F:     include/configs/colibri_vf.h
+F:     configs/colibri_vf_defconfig
diff --git a/board/toradex/colibri_vf/Makefile b/board/toradex/colibri_vf/Makefile
new file mode 100644 (file)
index 0000000..c7e5134
--- /dev/null
@@ -0,0 +1,7 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  := colibri_vf.o
diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
new file mode 100644 (file)
index 0000000..e7bc6c1
--- /dev/null
@@ -0,0 +1,361 @@
+/*
+ * Copyright 2015 Toradex, Inc.
+ *
+ * Based on vf610twr.c:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-vf610.h>
+#include <asm/arch/ddrmc-vf610.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <g_dnl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+                       PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
+                       PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
+                       PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+int dram_init(void)
+{
+       static const struct ddr3_jedec_timings timings = {
+               .tinit           = 5,
+               .trst_pwron      = 80000,
+               .cke_inactive    = 200000,
+               .wrlat           = 5,
+               .caslat_lin      = 12,
+               .trc             = 21,
+               .trrd            = 4,
+               .tccd            = 4,
+               .tfaw            = 20,
+               .trp             = 6,
+               .twtr            = 4,
+               .tras_min        = 15,
+               .tmrd            = 4,
+               .trtp            = 4,
+               .tras_max        = 28080,
+               .tmod            = 12,
+               .tckesr          = 4,
+               .tcke            = 3,
+               .trcd_int        = 6,
+               .tdal            = 12,
+               .tdll            = 512,
+               .trp_ab          = 6,
+               .tref            = 3120,
+               .trfc            = 64,
+               .tpdex           = 3,
+               .txpdll          = 10,
+               .txsnr           = 48,
+               .txsr            = 468,
+               .cksrx           = 5,
+               .cksre           = 5,
+               .zqcl            = 256,
+               .zqinit          = 512,
+               .zqcs            = 64,
+               .ref_per_zq      = 64,
+               .aprebit         = 10,
+               .wlmrd           = 40,
+               .wldqsen         = 25,
+       };
+
+       ddrmc_setup_iomux();
+
+       ddrmc_ctrl_init_ddr3(&timings, NULL, 1, 2);
+       gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+       return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+       static const iomux_v3_cfg_t uart_pads[] = {
+               NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
+               NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
+               NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL),
+               NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL),
+       };
+
+       imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+static void setup_iomux_enet(void)
+{
+       static const iomux_v3_cfg_t enet0_pads[] = {
+               NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL),
+               NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL),
+               NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL),
+               NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL),
+               NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL),
+               NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL),
+               NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL),
+               NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL),
+               NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL),
+               NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL),
+       };
+
+       imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
+}
+
+static void setup_iomux_i2c(void)
+{
+       static const iomux_v3_cfg_t i2c0_pads[] = {
+               VF610_PAD_PTB14__I2C0_SCL,
+               VF610_PAD_PTB15__I2C0_SDA,
+       };
+
+       imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
+}
+
+#ifdef CONFIG_NAND_VF610_NFC
+static void setup_iomux_nfc(void)
+{
+       static const iomux_v3_cfg_t nfc_pads[] = {
+               VF610_PAD_PTD23__NF_IO7,
+               VF610_PAD_PTD22__NF_IO6,
+               VF610_PAD_PTD21__NF_IO5,
+               VF610_PAD_PTD20__NF_IO4,
+               VF610_PAD_PTD19__NF_IO3,
+               VF610_PAD_PTD18__NF_IO2,
+               VF610_PAD_PTD17__NF_IO1,
+               VF610_PAD_PTD16__NF_IO0,
+               VF610_PAD_PTB24__NF_WE_B,
+               VF610_PAD_PTB25__NF_CE0_B,
+               VF610_PAD_PTB27__NF_RE_B,
+               VF610_PAD_PTC26__NF_RB_B,
+               VF610_PAD_PTC27__NF_ALE,
+               VF610_PAD_PTC28__NF_CLE
+       };
+
+       imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+       {ESDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+       /* eSDHC1 is always present */
+       return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+       static const iomux_v3_cfg_t esdhc1_pads[] = {
+               NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
+               NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
+               NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
+               NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
+               NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
+               NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
+       };
+
+       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+       imx_iomux_v3_setup_multiple_pads(
+               esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
+
+       return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
+static inline int is_colibri_vf61(void)
+{
+       struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
+
+       /*
+        * Detect board type by Level 2 Cache: VF50 don't have any
+        * Level 2 Cache.
+        */
+       return !!mscm->cpxcfg1;
+}
+
+static void clock_init(void)
+{
+       struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+       struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
+       u32 pfd_clk_sel, ddr_clk_sel;
+
+       clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
+                       CCM_CCGR0_UART0_CTRL_MASK);
+       clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
+                       CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
+       clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
+                       CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
+                       CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
+                       CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
+       clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
+                       CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
+       clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
+                       CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
+                       CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
+       clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
+                       CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
+       clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
+                       CCM_CCGR7_SDHC1_CTRL_MASK);
+       clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
+                       CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
+       clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
+                       CCM_CCGR10_NFC_CTRL_MASK);
+
+       clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
+                       ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE |
+                       ANADIG_PLL5_CTRL_DIV_SELECT);
+
+       if (is_colibri_vf61()) {
+               clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS |
+                               ANADIG_PLL2_CTRL_POWERDOWN,
+                               ANADIG_PLL2_CTRL_ENABLE |
+                               ANADIG_PLL2_CTRL_DIV_SELECT);
+       }
+
+       clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
+                       ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
+
+       clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
+                       CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
+
+       /* See "Typical PLL Configuration" */
+       if (is_colibri_vf61()) {
+               pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1);
+               ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0);
+       } else {
+               pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3);
+               ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1);
+       }
+
+       clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel |
+                       CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN |
+                       CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN |
+                       CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN |
+                       CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN |
+                       ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) |
+                       CCM_CCSR_SYS_CLK_SEL(4));
+
+       clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
+                       CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
+                       CCM_CACRR_ARM_CLK_DIV(0));
+       clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
+                       CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
+                       CCM_CSCMR1_NFC_CLK_SEL(0));
+       clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
+                       CCM_CSCDR1_RMII_CLK_EN);
+       clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
+                       CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
+                       CCM_CSCDR2_NFC_EN);
+       clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
+                       CCM_CSCDR3_NFC_PRE_DIV(5));
+       clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
+                       CCM_CSCMR2_RMII_CLK_SEL(2));
+}
+
+static void mscm_init(void)
+{
+       struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
+       int i;
+
+       for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+               writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+       if (phydev->drv->config)
+               phydev->drv->config(phydev);
+
+       return 0;
+}
+
+int board_early_init_f(void)
+{
+       clock_init();
+       mscm_init();
+
+       setup_iomux_uart();
+       setup_iomux_enet();
+       setup_iomux_i2c();
+#ifdef CONFIG_NAND_VF610_NFC
+       setup_iomux_nfc();
+#endif
+
+       return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+       struct src *src = (struct src *)SRC_BASE_ADDR;
+
+       /* Default memory arguments */
+       if (!getenv("memargs")) {
+               switch (gd->ram_size) {
+               case 0x08000000:
+                       /* 128 MB */
+                       setenv("memargs", "mem=128M");
+                       break;
+               case 0x10000000:
+                       /* 256 MB */
+                       setenv("memargs", "mem=256M");
+                       break;
+               default:
+                       printf("Failed detecting RAM size.\n");
+               }
+       }
+
+       if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
+                       == SRC_SBMR2_BMOD_SERIAL) {
+               printf("Serial Downloader recovery mode, disable autoboot\n");
+               setenv("bootdelay", "-1");
+       }
+
+       return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
+
+int board_init(void)
+{
+       struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
+
+       /* address of boot parameters */
+       gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+       /*
+        * Enable external 32K Oscillator
+        *
+        * The internal clock experiences significant drift
+        * so we must use the external oscillator in order
+        * to maintain correct time in the hwclock
+        */
+
+       setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
+
+       return 0;
+}
+
+int checkboard(void)
+{
+       if (is_colibri_vf61())
+               puts("Board: Colibri VF61\n");
+       else
+               puts("Board: Colibri VF50\n");
+
+       return 0;
+}
diff --git a/board/toradex/colibri_vf/imximage.cfg b/board/toradex/colibri_vf/imximage.cfg
new file mode 100644 (file)
index 0000000..8c52886
--- /dev/null
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2014 Toradex, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/imx-common/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION  2
+
+/* Boot Offset 0x400, valid for both SD and NAND boot */
+BOOT_OFFSET    FLASH_OFFSET_STANDARD
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
new file mode 100644 (file)
index 0000000..cef5a9e
--- /dev/null
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND"
+CONFIG_ARM=y
+CONFIG_TARGET_COLIBRI_VF=y
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
new file mode 100644 (file)
index 0000000..84ffbe8
--- /dev/null
@@ -0,0 +1,234 @@
+/*
+ * Copyright 2015 Toradex, Inc.
+ *
+ * Configuration settings for the Toradex VF50/VF61 module.
+ *
+ * Based on vf610twr.h:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_VF610
+#define CONFIG_SYS_THUMB_BUILD
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_USE_ARCH_MEMSET
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_FSL_LPUART
+#define LPUART_BASE                    UART0_BASE
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_SYS_UART_PORT           (0)
+#define CONFIG_BAUDRATE                        115200
+#define CONFIG_CMD_ASKENV
+
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_VF610_NFC
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           NFC_BASE_ADDR
+
+/* Dynamic MTD partition support */
+#define CONFIG_CMD_MTDPARTS    /* Enable 'mtdparts' command line support */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE      /* needed for mtdparts commands */
+#define MTDIDS_DEFAULT         "nand0=vf610_nfc"
+#define MTDPARTS_DEFAULT       "mtdparts=vf610_nfc:"           \
+                               "128k(vf-bcb)ro,"               \
+                               "1408k(u-boot)ro,"              \
+                               "512k(u-boot-env),"             \
+                               "-(ubi)"
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_ESDHC_NUM       1
+
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT3
+#define CONFIG_CMD_EXT4
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_UBI
+#define CONFIG_MTD_UBI_FASTMAP
+#define CONFIG_CMD_UBIFS       /* increases size by almost 60 KB */
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE                   ENET1_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE            RMII
+#define CONFIG_FEC_MXC_PHYADDR          0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+
+#define CONFIG_IPADDR          192.168.10.2
+#define CONFIG_NETMASK         255.255.255.0
+#define CONFIG_SERVERIP                192.168.10.1
+
+#define CONFIG_BOOTDELAY               1
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_LOADADDR                        0x80008000
+#define CONFIG_FDTADDR                 0x84000000
+
+/* We boot from the gfxRAM area of the OCRAM. */
+#define CONFIG_SYS_TEXT_BASE           0x3f408000
+#define CONFIG_BOARD_SIZE_LIMIT                524288
+
+#define SD_BOOTCMD \
+       "sdargs=root=/dev/mmcblk0p2 rw rootwait\0"      \
+       "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \
+       "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
+       "load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \
+       "load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
+       "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#define NFS_BOOTCMD \
+       "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
+       "nfsboot=run setup; " \
+       "setenv bootargs ${defargs} ${nfsargs} ${mtdparts} " \
+       "${setupargs} ${vidargs}; echo Booting from NFS...;" \
+       "dhcp ${kernel_addr_r} && "     \
+       "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
+       "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#define UBI_BOOTCMD    \
+       "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
+       "ubi.fm_autoconvert=1\0" \
+       "ubiboot=run setup; " \
+       "setenv bootargs ${defargs} ${ubiargs} ${mtdparts} "   \
+       "${setupargs} ${vidargs}; echo Booting from NAND...; " \
+       "ubi part ubi && ubifsmount ubi0:rootfs && " \
+       "ubifsload ${kernel_addr_r} /boot/${kernel_file} && " \
+       "ubifsload ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
+       "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       "kernel_addr_r=0x82000000\0" \
+       "fdt_addr_r=0x84000000\0" \
+       "kernel_file=zImage\0" \
+       "fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \
+       "fdt_board=eval-v3\0" \
+       "defargs=\0" \
+       "console=ttyLP0\0" \
+       "setup=setenv setupargs " \
+       "console=tty1 console=${console}" \
+       ",${baudrate}n8 ${memargs}\0" \
+       "setsdupdate=mmc rescan && set interface mmc && " \
+       "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
+       "source ${loadaddr}\0" \
+       "setusbupdate=usb start && set interface usb && " \
+       "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
+       "source ${loadaddr}\0" \
+       "setupdate=run setsdupdate || run setusbupdate\0" \
+       "mtdparts=" MTDPARTS_DEFAULT "\0" \
+       SD_BOOTCMD \
+       NFS_BOOTCMD \
+       UBI_BOOTCMD
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP            /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER         /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_PROMPT              "Colibri VFxx # "
+#undef CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE              256     /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE              \
+                       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS             16      /* max number of command args */
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START       0x80010000
+#define CONFIG_SYS_MEMTEST_END         0x87C00000
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+#define CONFIG_SYS_HZ                  1000
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE               (128 * 1024)    /* regular stack */
+
+/* Physical memory map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define PHYS_SDRAM                     (0x80000000)
+#define PHYS_SDRAM_SIZE                        (256 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV         0
+#define CONFIG_ENV_OFFSET              (12 * 64 * 1024)
+#define CONFIG_ENV_SIZE                        (8 * 1024)
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE                        (64 * 2048)
+#define CONFIG_ENV_RANGE               (4 * 64 * 2048)
+#define CONFIG_ENV_OFFSET              (12 * 64 * 2048)
+#endif
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#endif /* __CONFIG_H */