Each CPU needs to have its microcode loaded. Add support for this so that
all CPUs will have the same version.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
#include <asm/control_regs.h>
#include <asm/cpu.h>
#include <asm/lapic.h>
+#include <asm/microcode.h>
#include <asm/mp.h>
#include <asm/msr.h>
#include <asm/mtrr.h>
.align 4
_dt_ucode_base_size:
/* These next two fields are filled in by ifdtool */
+.globl ucode_base
+ucode_base: /* Declared in microcode.h */
.long 0 /* microcode base */
.long 0 /* microcode size */
if (!stack)
return -ENOMEM;
params->stack_top = (u32)(stack + size);
-
- params->microcode_ptr = 0;
+#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP)
+ params->microcode_ptr = ucode_base;
+ debug("Microcode at %x\n", params->microcode_ptr);
+#endif
params->msr_table_ptr = (u32)msr_save;
ret = save_bsp_msrs(msr_save, sizeof(msr_save));
if (ret < 0)
#ifndef __ASSEMBLY__
+/* This is a declaration for ucode_base in start.S */
+extern u32 ucode_base;
+
/**
* microcode_update_intel() - Apply microcode updates
*
temp_ram_init_params:
_dt_ucode_base_size:
/* These next two fields are filled in by ifdtool */
+.globl ucode_base
+ucode_base: /* Declared in micrcode.h */
.long 0 /* microcode base */
.long 0 /* microcode size */
.long CONFIG_SYS_MONITOR_BASE /* code region base */