dts: stm32mp1: clock tree update

- Add st,digbypass on clk_hse node (needed for board rev.C)
- MLAHB/AHB max frequency increased from 200 to 209MHz, with:
  - PLL3P set to 208.8MHz for MCU sub-system
  - PLL3Q set to 24.57MHz for 48kHz SAI/SPI2S
  - PLL3R set to 11.29MHz for 44.1kHz SAI/SPI2S
  - PLL4P set to 99MHz for SDMMC and SPDIFRX
  - PLL4Q set to 74.25MHz for EVAL board

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
index 4898483e1d16d35afd996a8fb85bccc6d7336749..70bbf66704262ba55eb4b2cb8a8d5369e58acfa9 100644 (file)
--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -39,6 +39,10 @@
        };
 };
 
+&clk_hse {
+       st,digbypass;
+};
+
 &uart4_pins_a {
        u-boot,dm-pre-reloc;
        pins1 {
@@ -68,7 +72,6 @@
        u-boot,dm-pre-reloc;
 };
 
-/* CLOCK init */
 &rcc {
        st,clksrc = <
                CLK_MPU_PLL1P
@@ -101,7 +104,7 @@
                CLK_FMC_ACLK
                CLK_QSPI_ACLK
                CLK_ETH_DISABLED
-               CLK_SDMMC12_PLL3R
+               CLK_SDMMC12_PLL4P
                CLK_DSI_DSIPLL
                CLK_STGEN_HSE
                CLK_USBPHY_HSE
@@ -110,7 +113,7 @@
                CLK_SPI45_HSI
                CLK_SPI6_HSI
                CLK_I2C46_HSI
-               CLK_SDMMC3_PLL3R
+               CLK_SDMMC3_PLL4P
                CLK_USBO_USBPHY
                CLK_ADC_CKPER
                CLK_CEC_LSE
@@ -121,17 +124,17 @@
                CLK_UART35_HSI
                CLK_UART6_HSI
                CLK_UART78_HSI
-               CLK_SPDIF_PLL3Q
+               CLK_SPDIF_PLL4P
                CLK_FDCAN_PLL4Q
                CLK_SAI1_PLL3Q
                CLK_SAI2_PLL3Q
                CLK_SAI3_PLL3Q
                CLK_SAI4_PLL3Q
-               CLK_RNG1_CSI
-               CLK_RNG2_CSI
+               CLK_RNG1_LSI
+               CLK_RNG2_LSI
                CLK_LPTIM1_PCLK1
                CLK_LPTIM23_PCLK3
-               CLK_LPTIM45_PCLK3
+               CLK_LPTIM45_LSE
        >;
 
        /* VCO = 1300.0 MHz => P = 650 (CPU) */
@@ -148,16 +151,16 @@
                u-boot,dm-pre-reloc;
        };
 
-       /* VCO = 786.4 MHz => P = 197, Q = 49, R = 98 */
+       /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
        pll3: st,pll@2 {
-               cfg = < 2 97 3 15 7 PQR(1,1,1) >;
-               frac = < 0x9ba >;
+               cfg = < 1 33 1 16 36 PQR(1,1,1) >;
+               frac = < 0x1a04 >;
                u-boot,dm-pre-reloc;
        };
 
-       /* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */
+       /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
        pll4: st,pll@3 {
-               cfg = < 5 126 8 8 8 PQR(1,1,1) >;
+               cfg = < 3 98 5 7 7 PQR(1,1,1) >;
                u-boot,dm-pre-reloc;
        };
 };

diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h
index 90ec780bfc68622f264e7e7c7e1e030c3b83cfba..4cdaf135829c6753865e1cffc95dcae2d92068b5 100644 (file)
--- a/include/dt-bindings/clock/stm32mp1-clks.h
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -248,7 +248,4 @@
 
 #define STM32MP1_LAST_CLK 232
 
-#define LTDC_K         LTDC_PX
-#define ETHMAC_K       ETHCK_K
-
 #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */