config TARGET_P4080DS
bool "Support P4080DS"
select PHYS_64BIT
+ select ARCH_P4080
config TARGET_P5020DS
bool "Support P5020DS"
config ARCH_P3041
bool
+config ARCH_P4080
+ bool
+
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
# various SoC specific assignments
obj-$(CONFIG_ARCH_P2041) += p2041_ids.o
obj-$(CONFIG_ARCH_P3041) += p3041_ids.o
-obj-$(CONFIG_PPC_P4080) += p4080_ids.o
+obj-$(CONFIG_ARCH_P4080) += p4080_ids.o
obj-$(CONFIG_PPC_P5020) += p5020_ids.o
obj-$(CONFIG_PPC_P5040) += p5040_ids.o
obj-$(CONFIG_PPC_T4240) += t4240_ids.o
obj-$(CONFIG_ARCH_P2020) += p2020_serdes.o
obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o
obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o
-obj-$(CONFIG_PPC_P4080) += p4080_serdes.o
+obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o
obj-$(CONFIG_PPC_P5020) += p5020_serdes.o
obj-$(CONFIG_PPC_P5040) += p5040_serdes.o
obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
0x50, 0x54, 0x58, 0x90, 0x94, 0x98
};
#endif
-#ifdef CONFIG_PPC_P4080
+#ifdef CONFIG_ARCH_P4080
static const uint8_t offsets[] = {
0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
};
x108 = 0x12;
#endif
-#ifdef CONFIG_PPC_P4080
+#ifdef CONFIG_ARCH_P4080
/*
* For P4080, the erratum document says that the value at offset 0x108
* should be 0x12 on rev2, or 0x1c on rev3.
}
#endif
-#if defined(CONFIG_PPC_P4080)
+#if defined(CONFIG_ARCH_P4080)
static void fdt_fixup_usb(void *fdt)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
{ 17, 163, FSL_SRDS_BANK_2 },
{ 18, 164, FSL_SRDS_BANK_2 },
{ 19, 165, FSL_SRDS_BANK_2 },
-#ifdef CONFIG_PPC_P4080
+#ifdef CONFIG_ARCH_P4080
{ 20, 170, FSL_SRDS_BANK_3 },
{ 21, 171, FSL_SRDS_BANK_3 },
{ 22, 172, FSL_SRDS_BANK_3 },
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
-#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
+#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_MAX_CPUS 8
#endif
#if defined(CONFIG_ARCH_P3041) || \
- defined(CONFIG_PPC_P4080) || \
+ defined(CONFIG_ARCH_P4080) || \
defined(CONFIG_PPC_P5020) || \
defined(CONFIG_PPC_P5040) || \
defined(CONFIG_ARCH_P2041)
#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
#define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
-#ifdef CONFIG_PPC_P4080
+#ifdef CONFIG_ARCH_P4080
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
#define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
# The P204x, P304x, and P5020 are the same
obj-$(CONFIG_ARCH_P2041) += p5020.o
obj-$(CONFIG_ARCH_P3041) += p5020.o
-obj-$(CONFIG_PPC_P4080) += p4080.o
+obj-$(CONFIG_ARCH_P4080) += p4080.o
obj-$(CONFIG_PPC_P5020) += p5020.o
obj-$(CONFIG_PPC_P5040) += p5040.o
obj-$(CONFIG_PPC_T1040) += t1040.o
* Also supports P4040 DS
*/
#define CONFIG_P4080DS
-#define CONFIG_PPC_P4080
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
CONFIG_PPC_B4420
CONFIG_PPC_B4860
CONFIG_PPC_CLUSTER_START
-CONFIG_PPC_P4080
CONFIG_PPC_P5020
CONFIG_PPC_P5040
CONFIG_PPC_SPINTABLE_COMPATIBLE