rockchip: Add support for veyron-mickey (Chromebit)
authorSimon Glass <sjg@chromium.org>
Sun, 13 Nov 2016 21:22:16 +0000 (14:22 -0700)
committerSimon Glass <sjg@chromium.org>
Sat, 26 Nov 2016 00:59:32 +0000 (17:59 -0700)
This adds support for the Asus Chromebit, and RK3288-based device designed
to plug directly into an HDMI monitor. The device tree file comes from
Linux v4.8.

Signed-off-by: Simon Glass <sjg@chromium.org>
arch/arm/dts/Makefile
arch/arm/dts/rk3288-veyron-mickey.dts [new file with mode: 0644]
arch/arm/mach-rockchip/rk3288-board-spl.c
arch/arm/mach-rockchip/rk3288/Kconfig
board/google/veyron/Kconfig
board/google/veyron/MAINTAINERS
configs/chromebit_mickey_defconfig [new file with mode: 0644]

index a345018510a91ec74d780a20aeddcad46647e630..fcbcdb5680df4e0c895278fb31e97adb70bd3453 100644 (file)
@@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
        rk3036-sdk.dtb \
        rk3288-firefly.dtb \
        rk3288-veyron-jerry.dtb \
+       rk3288-veyron-mickey.dtb \
        rk3288-rock2-square.dtb \
        rk3288-evb.dtb \
        rk3288-fennec.dtb \
diff --git a/arch/arm/dts/rk3288-veyron-mickey.dts b/arch/arm/dts/rk3288-veyron-mickey.dts
new file mode 100644 (file)
index 0000000..e0dc362
--- /dev/null
@@ -0,0 +1,277 @@
+/*
+ * Google Veyron Mickey Rev 0 board device tree source
+ *
+ * Copyright 2015 Google, Inc
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *  Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3288-veyron-chromebook.dtsi"
+
+/ {
+       model = "Google Mickey";
+       compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7",
+                    "google,veyron-mickey-rev6", "google,veyron-mickey-rev5",
+                    "google,veyron-mickey-rev4", "google,veyron-mickey-rev3",
+                    "google,veyron-mickey-rev2", "google,veyron-mickey-rev1",
+                    "google,veyron-mickey-rev0", "google,veyron-mickey",
+                    "google,veyron", "rockchip,rk3288";
+
+       vcc_5v: vcc-5v {
+               vin-supply = <&vcc33_sys>;
+       };
+
+       vcc33_io: vcc33_io {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc33_io";
+               regulator-always-on;
+               regulator-boot-on;
+               vin-supply = <&vcc33_sys>;
+       };
+};
+
+&cpu_thermal {
+       /delete-node/ trips;
+       /delete-node/ cooling-maps;
+
+       trips {
+               cpu_alert_almost_warm: cpu_alert_almost_warm {
+                       temperature = <63000>; /* millicelsius */
+                       hysteresis = <2000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu_alert_warm: cpu_alert_warm {
+                       temperature = <65000>; /* millicelsius */
+                       hysteresis = <2000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu_alert_almost_hot: cpu_alert_almost_hot {
+                       temperature = <80000>; /* millicelsius */
+                       hysteresis = <2000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu_alert_hot: cpu_alert_hot {
+                       temperature = <82000>; /* millicelsius */
+                       hysteresis = <2000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu_alert_hotter: cpu_alert_hotter {
+                       temperature = <84000>; /* millicelsius */
+                       hysteresis = <2000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu_alert_very_hot: cpu_alert_very_hot {
+                       temperature = <85000>; /* millicelsius */
+                       hysteresis = <2000>; /* millicelsius */
+                       type = "passive";
+               };
+               cpu_crit: cpu_crit {
+                       temperature = <90000>; /* millicelsius */
+                       hysteresis = <2000>; /* millicelsius */
+                       type = "critical";
+               };
+       };
+
+       cooling-maps {
+               /*
+                * After 1st level, throttle the CPU down to as low as 1.4 GHz
+                * and don't let the GPU go faster than 400 MHz.  Note that we
+                * won't throttle the GPU lower than 400 MHz due to CPU
+                * heat--we'll let the GPU do the rest itself.
+                */
+               cpu_warm_limit_cpu {
+                       trip = <&cpu_alert_warm>;
+                       cooling-device =
+                               <&cpu0 THERMAL_NO_LIMIT 4>;
+               };
+
+               /*
+                * Add some discrete steps to help throttling system deal
+                * with the fact that there are two passive cooling devices:
+                * the CPU and the GPU.
+                *
+                * - 1.2 GHz - 1.0 GHz (almost hot)
+                * - 800 MHz           (hot)
+                * - 800 MHz - 696 MHz (hotter)
+                * - 696 MHz - min     (very hot)
+                *
+                * Note:
+                * - 800 MHz appears to be a "sweet spot" for me.  I can run
+                *   some pretty serious workload here and be happy.
+                * - After 696 MHz we stop lowering voltage, so throttling
+                *   past there is less effective.
+                */
+               cpu_almost_hot_limit_cpu {
+                       trip = <&cpu_alert_almost_hot>;
+                       cooling-device =
+                               <&cpu0 5 6>;
+               };
+               cpu_hot_limit_cpu {
+                       trip = <&cpu_alert_hot>;
+                       cooling-device =
+                               <&cpu0 7 7>;
+               };
+               cpu_hotter_limit_cpu {
+                       trip = <&cpu_alert_hotter>;
+                       cooling-device =
+                               <&cpu0 7 8>;
+               };
+               cpu_very_hot_limit_cpu {
+                       trip = <&cpu_alert_very_hot>;
+                       cooling-device =
+                               <&cpu0 8 THERMAL_NO_LIMIT>;
+               };
+       };
+};
+
+&dmc {
+       rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
+               0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
+               0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
+               0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
+               0x8 0x1f4>;
+       rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
+               0x0 0xc3 0x6 0x2>;
+       rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 1>;
+};
+
+&emmc {
+       /delete-property/mmc-hs200-1_8v;
+};
+
+&i2c2 {
+       status = "disabled";
+};
+
+&i2c4 {
+       status = "disabled";
+};
+
+&i2s {
+       status = "okay";
+       clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
+       clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
+};
+
+&rk808 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
+       dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
+                   <&gpio7 15 GPIO_ACTIVE_HIGH>;
+
+       /delete-property/ vcc6-supply;
+       /delete-property/ vcc12-supply;
+
+       vcc11-supply = <&vcc33_sys>;
+
+       regulators {
+               /* vcc33_io is sourced directly from vcc33_sys */
+               /delete-node/ LDO_REG1;
+               /delete-node/ LDO_REG7;
+
+               /* This is not a pwren anymore, but the real power supply */
+               vdd10_lcd: LDO_REG7 {
+                       regulator-always-on;
+                       regulator-boot-on;
+                       regulator-min-microvolt = <1000000>;
+                       regulator-max-microvolt = <1000000>;
+                       regulator-name = "vdd10_lcd";
+                       regulator-suspend-mem-disabled;
+               };
+
+               vcc18_lcd: LDO_REG8 {
+                       regulator-always-on;
+                       regulator-boot-on;
+                       regulator-min-microvolt = <1800000>;
+                       regulator-max-microvolt = <1800000>;
+                       regulator-name = "vcc18_lcd";
+                       regulator-suspend-mem-disabled;
+               };
+       };
+};
+
+&pinctrl {
+       hdmi {
+               power_hdmi_on: power-hdmi-on {
+                       rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
+       pmic {
+               dvs_1: dvs-1 {
+                       rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
+               };
+
+               dvs_2: dvs-2 {
+                       rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
+               };
+       };
+};
+
+&sdmmc {
+       status = "disabled";
+};
+
+&sdio0 {
+       status = "disabled";
+};
+
+&sdmmc {
+       status = "disabled";
+};
+
+&spi0 {
+       status = "disabled";
+};
+
+&usb_host0_ehci {
+       status = "disabled";
+};
+
+&usb_host1 {
+       status = "disabled";
+};
+
+&vcc50_hdmi {
+       enable-active-high;
+       gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&power_hdmi_on>;
+};
index 185b5fdcf7286e4ff7c79b10da8dc6017443b16f..03ac0b42fb02af152731def5b2b7858280f4fd3d 100644 (file)
@@ -64,7 +64,8 @@ u32 spl_boot_device(void)
        }
 
 fallback:
-#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
+#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
+               defined(CONFIG_TARGET_CHROMEBIT_MICKEY)
        return BOOT_DEVICE_SPI;
 #endif
        return BOOT_DEVICE_MMC1;
index 30c557b8a3acb2f82419dfd5045cb1e401cc900c..204c1c7a9c2a56e698cab807fa48c15f7b8ad47f 100644 (file)
@@ -49,6 +49,15 @@ config TARGET_CHROMEBOOK_JERRY
          WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
          the keyboard and battery functions.
 
+config TARGET_CHROMEBIT_MICKEY
+       bool "Google/Rockchip Veyron-Mickey Chromebit"
+       help
+         Mickey is a small RK3288-based device with one USB 3.0 port, HDMI
+         and WiFi. It has a separate power port and is designed to connect
+         to the HDMI input of a monitor or TV. It has no internal battery.
+         Typically a USB hub or wireless keyboard/touchpad is used to get
+         keyboard and mouse access.
+
 config TARGET_ROCK2
        bool "Radxa Rock 2"
        help
index b1f51ce33dbb4b60ad0266df99cf80c5e6190ecd..a99190f3bd337fe9e85e355ec2331a6bfe7c1a14 100644 (file)
@@ -13,3 +13,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        def_bool y
 
 endif
+
+if TARGET_CHROMEBIT_MICKEY
+
+config SYS_BOARD
+       default "veyron"
+
+config SYS_VENDOR
+       default "google"
+
+config SYS_CONFIG_NAME
+       default "veyron"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+       def_bool y
+
+endif
index d641eed66ad3248ee7db7c060a0f47a8b2c67795..e44e1a9570d8584716fa37e1490758f2517d9845 100644 (file)
@@ -4,3 +4,10 @@ S:     Maintained
 F:     board/google/veyron/
 F:     include/configs/veyron.h
 F:     configs/chromebook_jerry_defconfig
+
+CHROMEBIT MICKEY BOARD
+M:     Simon Glass <sjg@chromium.org>
+S:     Maintained
+F:     board/google/veyron/
+F:     include/configs/veyron.h
+F:     configs/chromebit_mickey_defconfig
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
new file mode 100644 (file)
index 0000000..b118907
--- /dev/null
@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+# CONFIG_SPL_MMC_SUPPORT is not set
+CONFIG_ROCKCHIP_RK3288=y
+CONFIG_TARGET_CHROMEBIT_MICKEY=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DM_KEYBOARD=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+# CONFIG_SPL_SIMPLE_BUS is not set
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_I2C_MUX=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_CMD_CROS_EC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_PWRSEQ=y
+CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_ROCKCHIP_RK3288_PINCTRL=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_PMIC_RK808=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xff690000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_ROCKCHIP_SERIAL=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_ERRNO_STR=y
+CONFIG_SPL_OF_PLATDATA=y
+# CONFIG_SPL_OF_LIBFDT is not set