The earlier commit
f4fcba5c5ba ("clk: implement clk_set_defaults()")
which introduced the functionality for setting clock defaults such as
rates and parents will skip the processing when executing in a re-reloc
state. This for example can prevent the assigning of clock parents
when running in SPL code. Go ahead and remove this limitation.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
{
int ret;
- /* If this is running pre-reloc state, don't take any action. */
- if (!(gd->flags & GD_FLG_RELOC))
- return 0;
-
debug("%s(%s)\n", __func__, dev_read_name(dev));
ret = clk_set_default_parents(dev);