mips: mscc: Add generic GPIO control utility function

The GPIO control function can be used for controlling alternate
functions associated with a GPIO.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>

diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile
index 300c88b5cd04c768c32208d7027bd6c8567ba5bb..44538b7118bd66e9d79f6904891aa274d14ee214 100644 (file)
--- a/arch/mips/mach-mscc/Makefile
+++ b/arch/mips/mach-mscc/Makefile
@@ -2,5 +2,5 @@
 
 CFLAGS_cpu.o += -finline-limit=64000
 
-obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o
+obj-y += cpu.o dram.o reset.o phy.o gpio.o lowlevel_init.o
 obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o

diff --git a/arch/mips/mach-mscc/gpio.c b/arch/mips/mach-mscc/gpio.c
new file mode 100644 (file)
index 0000000..5e3a533
--- /dev/null
+++ b/arch/mips/mach-mscc/gpio.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+void mscc_gpio_set_alternate(int gpio, int mode)
+{
+       u32 mask = BIT(gpio);
+       u32 val0, val1;
+
+       val0 = readl(BASE_DEVCPU_GCB + GPIO_ALT(0));
+       val1 = readl(BASE_DEVCPU_GCB + GPIO_ALT(1));
+
+       if (mode == 1) {
+               val0 |= mask;
+               val1 &= ~mask;
+       } else if (mode == 2) {
+               val0 &= ~mask;
+               val1 |= mask;
+       } else if (mode == 3) {
+               val0 |= mask;
+               val1 |= mask;
+       } else {
+               val0 &= ~mask;
+               val1 &= ~mask;
+       }
+
+       writel(val0, BASE_DEVCPU_GCB + GPIO_ALT(0));
+       writel(val1, BASE_DEVCPU_GCB + GPIO_ALT(1));
+}

diff --git a/arch/mips/mach-mscc/include/mach/common.h b/arch/mips/mach-mscc/include/mach/common.h
index 92a055561ebde4bd4bd5cb67b8343357bb4f777b..d18ae78bfd1b47f06347847f03167e4e09222db3 100644 (file)
--- a/arch/mips/mach-mscc/include/mach/common.h
+++ b/arch/mips/mach-mscc/include/mach/common.h
@@ -45,4 +45,6 @@ int mscc_phy_wr(u32 miim_controller,
                u8 addr,
                u16 value);
 
+void mscc_gpio_set_alternate(int gpio, int mode);
+
 #endif                         /* __ASM_MACH_COMMON_H */

diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
index 8c0b612325efd65bb75596267ea0a10fa1c1c1bc..a06cf819b092bad58c64b6ecffe10a31e599ffb2 100644 (file)
--- a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
+++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
@@ -11,4 +11,6 @@
 #define PERF_SOFT_RST_SOFT_SWC_RST                        BIT(1)
 #define PERF_SOFT_RST_SOFT_CHIP_RST                       BIT(0)
 
+#define GPIO_ALT(x)                            (0x88 + 4 * (x))
+
 #endif

diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
index f8aa97ba2677c9b2ae3e6d90ce9c12eb4e149919..d3a76412e2e66c5b894abb7768651d5cc3f95722 100644 (file)
--- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
+++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
@@ -18,4 +18,6 @@
 
 #define PERF_GPIO_OE                                      0x44
 
+#define GPIO_ALT(x)                            (0x54 + 4 * (x))
+
 #endif