tegra20-trimslice.dtb \
tegra20-ventana.dtb \
tegra20-whistler.dtb \
- tegra20-colibri_t20_iris.dtb \
+ tegra20-colibri.dtb \
tegra30-apalis.dtb \
tegra30-beaver.dtb \
tegra30-cardhu.dtb \
--- /dev/null
+/dts-v1/;
+
+#include "tegra20.dtsi"
+
+/ {
+ model = "Toradex Colibri T20";
+ compatible = "toradex,t20", "nvidia,tegra20";
+
+ chosen {
+ stdout-path = &uarta;
+ };
+
+ aliases {
+ usb0 = "/usb@c5008000";
+ usb1 = "/usb@c5000000";
+ usb2 = "/usb@c5004000";
+ sdhci0 = "/sdhci@c8000600";
+ };
+
+ usb@c5000000 {
+ dr_mode = "otg";
+ };
+
+ usb@c5004000 {
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
+ };
+
+ usb@c5008000 {
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ nand-controller@70008000 {
+ nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
+ nvidia,width = <8>;
+ nvidia,timing = <15 100 25 80 25 10 15 10 100>;
+
+ nand@0 {
+ reg = <0>;
+ compatible = "nand-flash";
+ };
+ };
+
+ sdhci@c8000600 {
+ status = "okay";
+ cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ };
+};
+++ /dev/null
-/dts-v1/;
-
-#include "tegra20.dtsi"
-
-/ {
- model = "Toradex Colibri T20";
- compatible = "toradex,t20", "nvidia,tegra20";
-
- chosen {
- stdout-path = &uarta;
- };
-
- aliases {
- usb0 = "/usb@c5008000";
- usb1 = "/usb@c5000000";
- usb2 = "/usb@c5004000";
- sdhci0 = "/sdhci@c8000600";
- };
-
- usb@c5000000 {
- dr_mode = "otg";
- };
-
- usb@c5004000 {
- nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
- nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
- };
-
- usb@c5008000 {
- nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
- };
-
- nand-controller@70008000 {
- nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
- nvidia,width = <8>;
- nvidia,timing = <15 100 25 80 25 10 15 10 100>;
-
- nand@0 {
- reg = <0>;
- compatible = "nand-flash";
- };
- };
-
- sdhci@c8000600 {
- status = "okay";
- cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- };
-};
config TARGET_WHISTLER
bool "NVIDIA Tegra20 Whistler evaluation board"
-config TARGET_COLIBRI_T20_IRIS
+config TARGET_COLIBRI_T20
bool "Toradex Colibri T20 board"
endchoice
source "board/compulab/trimslice/Kconfig"
source "board/nvidia/ventana/Kconfig"
source "board/nvidia/whistler/Kconfig"
-source "board/toradex/colibri_t20_iris/Kconfig"
+source "board/toradex/colibri_t20/Kconfig"
endif
--- /dev/null
+if TARGET_COLIBRI_T20
+
+config SYS_BOARD
+ default "colibri_t20"
+
+config SYS_VENDOR
+ default "toradex"
+
+config SYS_CONFIG_NAME
+ default "colibri_t20"
+
+endif
--- /dev/null
+COLIBRI_T20
+M: Lucas Stach <dev@lynxeye.de>
+S: Maintained
+F: board/toradex/colibri_t20/
+F: include/configs/colibri_t20.h
+F: configs/colibri_t20_defconfig
+F: arch/arm/dts/tegra20-colibri.dtb
--- /dev/null
+#
+# (C) Copyright 2012 Lucas Stach
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(srctree)/board/nvidia/common/common.mk
+
+obj-y += colibri_t20.o
--- /dev/null
+/*
+ * Copyright (C) 2012 Lucas Stach
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/gpio.h>
+
+#ifdef CONFIG_TEGRA_MMC
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+ funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
+ pinmux_tristate_disable(PMUX_PINGRP_GMB);
+}
+#endif
+
+#ifdef CONFIG_TEGRA_NAND
+void pin_mux_nand(void)
+{
+ funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_TEGRA
+void pin_mux_usb(void)
+{
+ /* module internal USB bus to connect ethernet chipset */
+ funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
+
+ /* ULPI reference clock output */
+ pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+ pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
+
+ /* PHY reset GPIO */
+ pinmux_tristate_disable(PMUX_PINGRP_UAC);
+
+ /* VBus GPIO */
+ pinmux_tristate_disable(PMUX_PINGRP_DTE);
+
+ /* USB 1 aka Tegra USB port 3 VBus */
+ pinmux_tristate_disable(PMUX_PINGRP_SPIG);
+}
+#endif
+++ /dev/null
-if TARGET_COLIBRI_T20_IRIS
-
-config SYS_BOARD
- default "colibri_t20_iris"
-
-config SYS_VENDOR
- default "toradex"
-
-config SYS_CONFIG_NAME
- default "colibri_t20_iris"
-
-endif
+++ /dev/null
-COLIBRI_T20_IRIS BOARD
-M: Lucas Stach <dev@lynxeye.de>
-S: Maintained
-F: board/toradex/colibri_t20_iris/
-F: include/configs/colibri_t20_iris.h
-F: configs/colibri_t20_iris_defconfig
+++ /dev/null
-#
-# (C) Copyright 2012 Lucas Stach
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-include $(srctree)/board/nvidia/common/common.mk
-
-obj-y += colibri_t20_iris.o
+++ /dev/null
-/*
- * Copyright (C) 2012 Lucas Stach
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/funcmux.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch-tegra/board.h>
-#include <asm/gpio.h>
-
-#ifdef CONFIG_TEGRA_MMC
-/*
- * Routine: pin_mux_mmc
- * Description: setup the pin muxes/tristate values for the SDMMC(s)
- */
-void pin_mux_mmc(void)
-{
- funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
- pinmux_tristate_disable(PMUX_PINGRP_GMB);
-}
-#endif
-
-#ifdef CONFIG_TEGRA_NAND
-void pin_mux_nand(void)
-{
- funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
-}
-#endif
-
-#ifdef CONFIG_USB_EHCI_TEGRA
-void pin_mux_usb(void)
-{
- /* module internal USB bus to connect ethernet chipset */
- funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
-
- /* ULPI reference clock output */
- pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
- pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
-
- /* PHY reset GPIO */
- pinmux_tristate_disable(PMUX_PINGRP_UAC);
-
- /* VBus GPIO */
- pinmux_tristate_disable(PMUX_PINGRP_DTE);
-
- /* USB 1 aka Tegra USB port 3 VBus */
- pinmux_tristate_disable(PMUX_PINGRP_SPIG);
-}
-#endif
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_COLIBRI_T20=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri"
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TEGRA=y
-CONFIG_TEGRA20=y
-CONFIG_TARGET_COLIBRI_T20_IRIS=y
-CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri_t20_iris"
--- /dev/null
+/*
+ * Copyright (C) 2012 Lucas Stach
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra20-common.h"
+
+/* High-level configuration options */
+#define V_PROMPT "Colibri T20 # "
+#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T20"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_TEGRA_UARTA_SDIO1
+#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+
+/* SD/MMC support */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* USB host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_ULPI
+#define CONFIG_USB_ULPI_VIEWPORT
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (SZ_2M)
+#undef CONFIG_ENV_SIZE /* undef size from tegra20-common.h */
+#define CONFIG_ENV_SIZE (SZ_64K)
+
+/* Debug commands */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CACHE
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (C) 2012 Lucas Stach
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "tegra20-common.h"
-
-/* High-level configuration options */
-#define V_PROMPT "Tegra20 (Colibri) # "
-#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T20 on Iris"
-
-/* Board-specific serial config */
-#define CONFIG_TEGRA_ENABLE_UARTA
-#define CONFIG_TEGRA_UARTA_SDIO1
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-
-/* SD/MMC support */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
-#define CONFIG_CMD_MMC
-
-/* USB host support */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_TEGRA
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-#define CONFIG_CMD_USB
-
-/* USB networking support */
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-
-/* NAND support */
-#define CONFIG_CMD_NAND
-#define CONFIG_TEGRA_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET (SZ_2M)
-#undef CONFIG_ENV_SIZE /* undef size from tegra20-common.h */
-#define CONFIG_ENV_SIZE (SZ_64K)
-
-/* Debug commands */
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_CACHE
-
-#include "tegra-common-post.h"
-
-#endif /* __CONFIG_H */
run_list_real 1996 2000 +4
do_nandboot 760 756 -4
do_mem_crc 168 68 -100
- colibri_t20_iris: all -9 rodata -29 text +20
+ colibri_t20 : all -9 rodata -29 text +20
u-boot: add: 1/0, grow: 2/-3 bytes: 140/-112 (28)
function old new delta
hash_command 80 160 +80
projects / oweals / u-boot.git / commitdiff