sunxi: Add support for UART0 in PB pin group on A33

The A33 adds a pinmux function for UART0 in the PB pin group.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 1c268656ff1829fb51b4fc364a2f8a027d004400..5f39aa07cfb03dc66c35cc8b973f14ee49aeeda1 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -64,6 +64,10 @@ static int gpio_init(void)
        sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
        sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
        sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
+       sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
+       sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
+       sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
        sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
        sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 496295d35735ebc2ca468ff184a79a4c3c8fb70f..8e67b3bcb87d0fe411fb95588fe85e1fbcd22f27 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -156,6 +156,7 @@ enum sunxi_gpio_number {
 #define SUN4I_GPB_UART0                2
 #define SUN5I_GPB_UART0                2
 #define SUN8I_GPB_UART2                2
+#define SUN8I_A33_GPB_UART0    3
 
 #define SUNXI_GPC_SDC2         3
 #define SUN6I_GPC_SDC3         4