driver/ddr/fsl: Add sync of refresh

Add sync of refresh for multiple DDR controllers. DDRC initialization
needs to complete first. Code is re-ordered to keep refresh close.

Signed-off-by: York Sun <yorksun@freescale.com>

diff --git a/README b/README
index ba57dc5617a3823ca8345b5f5751035a046cbcc5..6800b959ca558e18b5e8ee7871f53bf5990fc89d 100644 (file)
--- a/README
+++ b/README
@@ -4916,6 +4916,9 @@ Low Level (hardware related) configuration options:
 - CONFIG_FSL_DDR_INTERACTIVE
                Enable interactive DDR debugging. See doc/README.fsl-ddr.
 
+- CONFIG_FSL_DDR_SYNC_REFRESH
+               Enable sync of refresh for multiple controllers.
+
 - CONFIG_SYS_83XX_DDR_USES_CS0
                Only for 83xx systems. If specified, then DDR should
                be configured using CS0 and CS1 instead of CS2 and CS3.

diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index f49939b1359c39cdbb7bab9b1721806e3b0182d0..b72b24290ec911acadfa9186062fbd08c72c7eac 100644 (file)
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -692,6 +692,10 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
                }
        }
 
+#ifdef CONFIG_FSL_DDR_SYNC_REFRESH
+       fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl);
+#endif
+
 #ifdef CONFIG_PPC
        /* program LAWs */
        for (i = first_ctrl; i <= last_ctrl; i++) {

diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index ad569de27a4a867e3765635719b7e71b99b8b2bc..664081b1b8369ae57fb7e32634ee2a839711c9d1 100644 (file)
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -308,3 +308,58 @@ void board_add_ram_info(int use_default)
 {
        detail_board_ddr_info();
 }
+
+#ifdef CONFIG_FSL_DDR_SYNC_REFRESH
+#define DDRC_DEBUG20_INIT_DONE 0x80000000
+#define DDRC_DEBUG2_RF         0x00000040
+void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
+                                unsigned int last_ctrl)
+{
+       unsigned int i;
+       u32 ddrc_debug20;
+       u32 ddrc_debug2[CONFIG_NUM_DDR_CONTROLLERS] = {};
+       u32 *ddrc_debug2_p[CONFIG_NUM_DDR_CONTROLLERS] = {};
+       struct ccsr_ddr __iomem *ddr;
+
+       for (i = first_ctrl; i <= last_ctrl; i++) {
+               switch (i) {
+               case 0:
+                       ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+                       break;
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+               case 1:
+                       ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+                       break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+               case 2:
+                       ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+                       break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+               case 3:
+                       ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
+                       break;
+#endif
+               default:
+                       printf("%s unexpected ctrl = %u\n", __func__, i);
+                       return;
+               }
+               ddrc_debug20 = ddr_in32(&ddr->debug[19]);
+               ddrc_debug2_p[i] = &ddr->debug[1];
+               while (!(ddrc_debug20 & DDRC_DEBUG20_INIT_DONE)) {
+                       /* keep polling until DDRC init is done */
+                       udelay(100);
+                       ddrc_debug20 = ddr_in32(&ddr->debug[19]);
+               }
+               ddrc_debug2[i] = ddr_in32(&ddr->debug[1]) | DDRC_DEBUG2_RF;
+       }
+       /*
+        * Sync refresh
+        * This is put together to make sure the refresh reqeusts are sent
+        * closely to each other.
+        */
+       for (i = first_ctrl; i <= last_ctrl; i++)
+               ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]);
+}
+#endif /* CONFIG_FSL_DDR_SYNC_REFRESH */

diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h
index 96fde91687dc74c4f1f5cc1109673af79063dffd..feccef9c9cd16b2311d60ed82c4a742bf7389b0f 100644 (file)
--- a/include/fsl_ddr.h
+++ b/include/fsl_ddr.h
@@ -118,6 +118,8 @@ void fsl_ddr_set_lawbar(
                const common_timing_params_t *memctl_common_params,
                unsigned int memctl_interleaved,
                unsigned int ctrl_num);
+void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
+                                unsigned int last_ctrl);
 
 int fsl_ddr_interactive_env_var_exists(void);
 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);